Abstract
This chapter addresses many important topics such as testing the test-bench, triggering concurrent assertions from procedural blocks, calling subroutines, sequences as formal arguments, as antecedent and as triggering condition in a sensitivity list. It also describes further nuances such as how to design “variable delay” using a “counter,” effects of blocking nature of an “action” (pass/fail) block, cyclic dependencies, vacuous pass of an assertion, empty sequences, etc.
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Mehta, A.B. (2020). Important Topics. In: System Verilog Assertions and Functional Coverage. Springer, Cham. https://doi.org/10.1007/978-3-030-24737-9_17
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DOI: https://doi.org/10.1007/978-3-030-24737-9_17
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Publisher Name: Springer, Cham
Print ISBN: 978-3-030-24736-2
Online ISBN: 978-3-030-24737-9
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