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Design and Simulation of Array Cells of Mixed Sensor Processors for Intensity Transformation and Analog-Digital Coding in Machine Vision

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Abstract

The urgent need to create video sensors and processors for parallel (simultaneous by pixel) image processing with advanced functionality and multichannel picture outputs is shown in the chapter. We consider perspective spheres and areas of application of such sensor processors, in particular, for hardware high-performance architectures of neural networks, convolutional neural structures, parallel matrix-matrix multipliers, and special processor systems. We show and analyze the theoretical foundations, the mathematical apparatus of the matrix and continuous logic, and their basic operations, show their functional completeness, and evaluate their advantages and prospects for application in the design of biologically inspired devices and systems for processing and analysis of array signals. We show that some functions of continuous logic, including operations of normalized equivalence of vector and matrix signals, the operation of a limited difference in continuous logic, are a powerful basis for designing improved smart micro-cells for analog transformations and analog-digital encodings. In the next sections of the chapter, we consider in more detail the design and modeling aspects of such micro-basic cells and continuously logical high-speed ADCs based on them. The picture-type ADC consists of an array of parallel operating channels, each of which is a basic microcell or a set of them. The basic microcell of a 2D ADC structure consists of several digital-analog cells (DC), which is made on 15–35 CMOS transistors. For an iterative type ADC, only one DC cell is needed, which is DC-(G), and it additionally contains a sample and hold device (SHD). In this case, the entire base microcell can be performed on just 35 CMOS transistors. A single ADC channel cell with iteration has a serial-parallel output code. For a non-iterative-type ADC, its base microcell may consist of such a quantity of DC, which depends on the digit capacity of the code. To simulate the proposed schemes, we used OrCAD, and the results are presented below. Conversion time with 6–8-bit binary codes or Gray codes and an input photocurrent range of 0.1–24 μA is 20–30 ns at a supply voltage of 1.8–3.3 V. If the maximum input current is 4 μA, then for ADC with iteration, total power consumption was only 50–100 μW. Low power consumption at such a supply voltage and good dynamic characteristics (the digitization frequency even for 1.5 μm CMOS technologies is 40–50 MHz) shows good prospects since the structure of the linear array of ADCs and its microcells is very simple. The conversion frequency can be increased ten times with more advanced CMOS transistors. Thus, the proposed ADC based on CL BC and CM are promising for creating photoelectric structures with matrix operands, digital optoelectronic processors, linear and matrix image processors (IP), and other neural-like structures that are necessary for neural networks and neuro fuzzy controllers. In the chapter, we consider a generalized method of designing devices for nonlinear transformation of the photocurrent intensity using a set of similar basic modified cells and their circuits implemented using traditional CMOS technology. To implement the required nonlinear transformation function, we use the decomposition method. The type of synthesized functions is determined by the choice of suitable parameters, which are specified as constants or as parameters with which you can choose or change the type of nonlinear transformation. In this chapter, we also show the need for different types of nonlinear intensity conversion of photocurrents and different codes (gray, binary) for AD conversion in such parallel sensor devices and systems, especially for implementing various types of activation functions in hardware implementations of neural networks, consider the use of such parallel matrix arrays to create progressive IP and neural networks (NN). The cells offered by us have a low supply voltage of 1.8–3.3 V, low power consumption (microwatts), the conversion time is less than 1 μs, and consist of several dozen transistors. We also consider the cells for the implementation of various neuron activation functions in neural networks and transient nonlinear conversion with characteristics of S-, N-, and λ-types. In conclusion, we make estimates and show the prospects for such approaches to the design of sensor processors.

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Abbreviations

AAM:

Auto-associative memory

ABC:

Analog-digital basic cell

ADC:

Analog–to-digital converter

AM:

Associative memory

BC:

Basic cell

BIA:

Binary image algebra

CCCA:

Current-controlled current amplifiers on current mirror multipliers

CDNE:

Complementary double NE

CL:

Continuous logic

CLC:

Continuous logic cell

CLEM:

Continuous logical equivalence model

CLF:

Continuous logic function

CM:

Current mirror

CMM:

Current multiplier mirror

CMOS:

Complementary metal-oxide-semiconductor

CNN:

Convolutional neural network

DAC:

Digital-to-analog converter

DC:

Digital-analog cell

DOEP:

Digital optoelectronic processor

EM:

Equivalence model

EQ_CL:

Equivalent continuous-logical

FPAA:

Field-programmable analog array

G:

Gray

HAM:

Hetero-associative memory

IP:

Image processor

MAAM:

Multi-port AAM

MHAM:

Multi-port hetero-associative memory

MIMO:

Multi-input and multi-output

MLA:

Array of microlenses

NE:

Neural element

NEq:

Normalized equivalence

NEqs:

Neuron equivalentors

NN:

Neural network

NnEq:

Normalized nonequivalence

NSEqF:

Normalized spatial equivalence function

OE-VLSI:

Optoelectronic very large scale integration

SD_NEF:

Spatially dependent normalized equivalence function

SHD:

Sample and hold device

SI ЕМ АM:

Spatially invariant equivalence model of associative memory

SLECNS:

Self-learning equivalent convolutional neural structure

SMC_ADC:

Multichannel sensory analog-to-digital converter

TC:

Transfer characteristics

TPCA:

Time-pulse-coded architecture

ULE:

Universal (multifunctional) logical element

VMO:

Vector or matrix organization

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Authors and Affiliations

  1. Vinnytsia National Technical University, Vinnytsia, Ukraine

    Vladimir G. Krasilenko, Alexander A. Lazarev & Diana V. Nikitovich

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  1. Vladimir G. Krasilenko
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  2. Alexander A. Lazarev
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Editors and Affiliations

  1. Universidad Autónoma de Baja California, Mexicali, Baja California, Mexico

    Oleg Sergiyenko

  2. Universidad Autónoma de Baja California, Mexicali, Baja California, Mexico

    Wendy Flores-Fuentes

  3. Leuphana University of Lueneburg, Lueneburg, Low Saxony, Niedersachsen, Germany

    Paolo Mercorelli

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Krasilenko, V.G., Lazarev, A.A., Nikitovich, D.V. (2020). Design and Simulation of Array Cells of Mixed Sensor Processors for Intensity Transformation and Analog-Digital Coding in Machine Vision. In: Sergiyenko, O., Flores-Fuentes, W., Mercorelli, P. (eds) Machine Vision and Navigation. Springer, Cham. https://doi.org/10.1007/978-3-030-22587-2_4

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  • Online ISBN: 978-3-030-22587-2

  • eBook Packages: EngineeringEngineering (R0)

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