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Design and Aging Challenges in FinFET Circuits and Internet of Things (IoT) Applications

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Circadian Rhythms for Future Resilient Electronic Systems

Abstract

The advent of FinFETs has extended the CMOS lifeline by a few more technology nodes (5 nm and even 3 nm are now under development), so it is critical for digital circuit designers and researchers to understand some of the fundamental differences between advanced FinFET nodes and older planar devices, along with the associated challenges (e.g., design and aging challenges) in the forthcoming sub-10 nm regime. This chapter consists of two major thrusts. In the first thrust, we present a comprehensive study that compares multiple technology nodes spanning from old planar devices to the most advanced FinFET nodes. This study adds to the FinFET design knowledge base and helps designers gain a thorough understanding of various design challenges. The second trust mainly looks at the impact of FinFET aging within the context of Internet of Things (IoT). Through extensive simulations with foundry-provided FinFET aging models, we conclude that aging can severely affect certain category of IoT applications; hence, this aspect needs to be incorporated in the design cycle to meet the overall system lifetime targets. Several candidate techniques against aging are also presented for designing robust IoT chips that perform faster, consume lower power, and last longer than without the use of these techniques.

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Notes

  1. 1.

    This chapter focuses mostly on transistor aging (especially BTI and HCI). Battery aging, socket (and holder solder) aging in IoT devices are also important, but they are beyond the scope of our discussion.

  2. 2.

    In advanced technology nodes the “numbering” scheme is somewhat “fuzzy”; while in older technologies the node “number” used to denote the smallest feature size—usually the transistor gate length, in modern technologies the node number does not refer to any one feature in the process, and foundries use slightly different conventions. In this chapter, we use 1× to denote the 14–16 nm FinFET nodes offered by several foundries.

  3. 3.

    Here PDN refers to the pull down network, in the rest of book, PDN stands for power delivery network.

  4. 4.

    This book focuses on circuit aging. Battery aging and socket (and holder solder) aging are out of the scope of discussion.

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    Xinfei Guo & Mircea R. Stan

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Guo, X., Stan, M.R. (2020). Design and Aging Challenges in FinFET Circuits and Internet of Things (IoT) Applications. In: Circadian Rhythms for Future Resilient Electronic Systems. Springer, Cham. https://doi.org/10.1007/978-3-030-20051-0_6

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