Abstract
This chapter will present the future research work direction regarding calibration and architecture improvements. Two possible calibration schemes are presented and their advantages and drawbacks are discussed. A conversion architecture that solves the shortcomings identified in the architecture presented in this thesis is presented and its mode of operation is detailed. The concluding remarks will be drawn at the end of the chapter.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Y.-H. Seo, J.-S. Kim, H.-J. Park, J.-Y. Sim, A 1.25 ps resolution 8b cyclic TDC in 0.13 µm CMOS. IEEE J. Solid-State Circuits 47(3), 736–743 (2012)
Y.-H. Seo, J.-S. Kim, H.-J. Park, J.-Y. Sim, A 0.63 ps Resolution, 11b Pipeline TDC in 0.13 µm CMOS, in Symposium on VLSI Circuits (Honolulu, HI, 2011), pp. 152–153
H. Huang, C. Sechen, A 22 mW 227 Msps 11b self-tuning ADC based on time-to-digital conversion, in IEEE Dallas Circuits and Systems Workshop (DCAS) (Richardson, TX, 2009), pp. 1–4
M. Park, M.H. Perrott, A single-slope 80 MS/s ADC using Two-Step Time-to-Digital Conversion, in IEEE International Symposium on Circuits and Systems (Taipei, 2009), pp. 1125–1128
M.Z. Straayer, M.H. Perrott, An efficient high-resolution 11-bit noise-shaping multipath gated ring oscillator TDC, in IEEE Symposium on VLSI Circuits (Honolulu, HI, 2008), pp. 82–83
S. Srinivasan, S. Mathew, V. Erraguntla, R. Krishnamurthy, A 4 Gbps 0.57 pJ/bit Process-voltage-temperature variation tolerant all-digital true random number generator in 45 nm CMOS, in 2009 22nd International Conference on VLSI Design (New Delhi, 2009), pp. 301–306
S.K. Mathew et al., 2.4 Gbps, 7 mW all-digital PVT-variation tolerant true random number generator for 45 nm CMOS high-performance microprocessors. IEEE J. Solid-State Circuits 47(11), 2807–2821 (2012)
S.K. Mathew et al., µRNG: A 300–950 mV, 323 Gbps/W all-digital full-entropy true random number generator in 14 nm FinFET CMOS. IEEE J. Solid-State Circuits 51(7), 1695–1704 (2016)
P.M. Figueiredo, J.C. Vital, Offset cancellation methods, in Offset Reduction Techniques in High-Speed Analog-to-Digital Converters: Analysis, Design and Tradeoffs, ed. by M. Ismail (Springer, 2009), Chap. 5, pp. 261–304
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
Copyright information
© 2019 Springer Nature Switzerland AG
About this chapter
Cite this chapter
Santos, M., Guilherme, J., Horta, N. (2019). Future Work and Conclusions. In: Logarithmic Voltage-to-Time Converter for Analog-to-Digital Signal Conversion. Lecture Notes in Electrical Engineering, vol 558. Springer, Cham. https://doi.org/10.1007/978-3-030-15978-8_7
Download citation
DOI: https://doi.org/10.1007/978-3-030-15978-8_7
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-15977-1
Online ISBN: 978-3-030-15978-8
eBook Packages: EngineeringEngineering (R0)