Abstract
This chapter covers the memristive HTM implementations on mixed-signal and analog hardware. Most of the implemented memristive systems are based on modified HTM algorithm. The HTM is often used as a feature encoding and feature extraction tool, and these features are then used with conventional nearest neighbor method for classification.
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References
Fan D, Sharad M, Sengupta A, Roy K (2016) Hierarchical temporal memory based on spin-neurons and resistive memory for energy-efficient brain-inspired computing. IEEE Trans Neural Netw Learn Syst 27(9):1907–1919
Hawkins J, George D (2006) Hierarchical temporal memory: Concepts, theory and terminology. Technical report, Numenta
Hawkins J, Ahmad S, Dubinsky D (2010) Hierarchical temporal memory including htm cortical learning algorithms. Technical report, Numenta, Inc, Palto Alto. http://www.numenta.com/htmoverview/education/HTM_CorticalLearningAlgorithms.pdf
Ibrayev T, Krestinskaya O, James AP (2017) Design and implication of a rule based weight sparsity module in htm spatial pooler. In: 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS). IEEE, pp 274–277
Ibrayev T, James AP, Merkel C, Kudithipudi D (2016) A design of htm spatial pooler for face recognition using memristor-cmos hybrid circuits. In: 2016 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, pp 1254–1257
Ibrayev T, Myrzakhan U, Krestinskaya O, Irmanova A, James AP (2018) On-chip face recognition system design with memristive hierarchical temporal memory. J Intell Fuzzy Syst 34(3):1393–1402
Irmanova A, Ibrayev T, James AP (2017) Discrete-level memristive circuits for htm-based spatiotemporal data classification system. IET Cyber Phys Syst Theory Appl 3(1):34–43
James AP, Fedorova I, Ibrayev T, Kudithipudi D (2017) Htm spatial pooler with memristor crossbar circuits for sparse biometric recognition. IEEE Trans Biomed Circuits Syst 11(3):640–651
James A, Ibrayev T, Krestinskaya O, Dolzhikova I (2018) Introduction to memristive htm circuits. In: Memristor and Memristive Neural Networks. InTech
Krestinskaya O, James AP (2018) Feature extraction without learning in an analog spatial pooler memristive-cmos circuit design of hierarchical temporal memory. Analog Integr Circuits Signal Process 95(3):457–465
Krestinskaya O, Dolzhikova I, James AP (2018) Hierarchical temporal memory using memristor networks: a survey. IEEE Trans Emerg Top Comput Intell 2(5):380–395. https://doi.org/10.1109/TETCI.2018.2838124
Krestinskaya O, Ibrayev T, James AP (2018) Hierarchical temporal memory features with memristor logic circuits for pattern recognition. IEEE Trans Comput Aided Des Integr Circuits Syst 37(6):1143–1156
Krestinskaya O, James AP, Chua LO (2018) Neuro-memristive circuits for edge computing: a review. arXiv preprint arXiv:1807.00962
Lazzaro J, Ryckebusch S, Mahowald MA, Mead CA (1989) Winner-take-all networks of o (n) complexity. In: Advances in Neural Information Processing Systems, pp 703–711
Zyarah AM, Kudithipudi D (2015) Reconfigurable hardware architecture of the spatial pooler for hierarchical temporal memory. In: 2015 28th IEEE International System-on-Chip Conference (SOCC). IEEE, pp 143–153
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Chapter Highlights
Chapter Highlights
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Most of the hardware implementations of HTM with memristive devices are based on the modification of original HTM algorithm.
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HTM SP can be used for both: original HTM and for the extraction of meaningful features from input data in the traditional nearest neighbor classification approach.
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Even thought several HTM implementations have been proposed in recent years [1, 8, 12], the full on-chip hardware implementation of original HTM algorithm is an open problem.
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Krestinskaya, O., Dolzhikova, I., James, A.P. (2020). Memristive Hierarchical Temporal Memory. In: James, A. (eds) Deep Learning Classifiers with Memristive Networks. Modeling and Optimization in Science and Technologies, vol 14. Springer, Cham. https://doi.org/10.1007/978-3-030-14524-8_14
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DOI: https://doi.org/10.1007/978-3-030-14524-8_14
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