Abstract
The paper shows the radiation effects on 65 nm standard CMOS technology and RHBD (Radiation Hardening By Design) techniques developed to reduce the mosfets performance degradation. The paper is focused on the techniques to address extremely high Total Ionization Dose (TID) up to 1 Grad, which is the level required for the planned upgrade of the CERN’s LHC (HL-LHC). Today, only few data of single mosfets measurement at 1 Grad are presented in literature. These data are collected and transistors models are developed to presents, in this paper, the first system simulation results at 1 Grad conditions. As case of study, the performance reduction of two full-custom D flip-flops are presented, highlighting the robustness against radiation of CML technology for high-speed applications (10 Gbps).
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Ciarpi, G., Saponara, S., Magazzù, G., Palla, F. (2019). Radiation Hardness by Design Techniques for 1 Grad TID Rad-Hard Systems in 65 nm Standard CMOS Technologies. In: Saponara, S., De Gloria, A. (eds) Applications in Electronics Pervading Industry, Environment and Society. ApplePies 2018. Lecture Notes in Electrical Engineering, vol 573. Springer, Cham. https://doi.org/10.1007/978-3-030-11973-7_31
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DOI: https://doi.org/10.1007/978-3-030-11973-7_31
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