Abstract
The work analyses the cybersecurity weakness in state-of-art automotive in-vehicle networks and discusses possible countermeasures at architecture level. Due to stringent real-time constraints (throughput and latency) of fail-safe automotive applications, hardware accelerators are needed. A hardware accelerator design for AES (Advanced Encryption Standard)-128/256 calculation, the latter being already considered post-quantum resistant, is also presented together with implementation results in FPGA and 45 nm CMOS technology.
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This work has been partially supported by PRA2017 and EPI H2020 projects.
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Baldanzi, L., Crocetti, L., Bertolucci, M., Fanucci, L., Saponara, S. (2019). Analysis of Cybersecurity Weakness in Automotive In-Vehicle Networking and Hardware Accelerators for Real-Time Cryptography. In: Saponara, S., De Gloria, A. (eds) Applications in Electronics Pervading Industry, Environment and Society. ApplePies 2018. Lecture Notes in Electrical Engineering, vol 573. Springer, Cham. https://doi.org/10.1007/978-3-030-11973-7_2
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