Abstract
This paper presents a software that generates code that implements a microprocessor simulator based on features defined by user. Software receives a set of microprocessor architecture description that includes: number of cores, operations to be executed in the ALU, cache memory details, and number of registers, among others. After configuration, the software generates Java code that implements the microprocessor simulator described. Software can generates more than forty different codes depending on the configurations defined. Each simulator follows a standard four stages pipeline: fetch, decode, execute and store. Code generator has been used as a learning tool in an undergraduate course with interesting effects in the student’s learning process. Preliminary results show that students understand better how a microprocessor works and they felt ready to propose new microprocessor architectures.
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Acknowledgements
Authors would like to thank to students from Facultad de Ingeniería en Electrónica y Comunicaciones, Universidad Veracruzana and students from Centro de Investigación en Cómputo, Instituto Politécnico Nacional who participated during the research activities. Likewise, authors would like to thank to both institutions authorities who make possible this research collaboration.
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Cristóbal-Salas, A. et al. (2019). Automatic Code Generator for a Customized High Performance Microprocessor Simulator. In: Torres, M., Klapp, J., Gitler, I., Tchernykh, A. (eds) Supercomputing. ISUM 2018. Communications in Computer and Information Science, vol 948. Springer, Cham. https://doi.org/10.1007/978-3-030-10448-1_2
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DOI: https://doi.org/10.1007/978-3-030-10448-1_2
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