Abstract
Fault-tolerant mechanisms have been an essential part of the electronic equipment in extreme environments such as high voltage, extreme temperature and strong electromagnetic environment etc. Accordingly, how to improve the robustness and disturbance rejection performance of the circuit has become the primary problem in recent years. In this paper, a heterogeneous evaluation method based on relational analysis is proposed. It uses genetic algorithm and evolutionary hardware to get the required sub-circuit structures and uses relational strategy to evaluate heterogeneous degree of redundant circuit system. Finally, the sub-structures with large heterogeneous degree are selected to build redundant circuit system. In the experiments, we designed short-circuit fault and parameter drift fault to validate the heterogeneous evaluation method. The experimental results show this method can not only enhance the heterogeneous degree, but also maintain high robustness. Compared with random heterogeneous redundant system and homogeneous redundant system, the Average Fault-free Probability of redundant fault-tolerant circuit system based on relational method is 8.9% and 21.7% higher respectively in short-circuit fault experiments, and it is 9.1% and 23.9% higher respectively in parameter drift fault experiments.
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20 January 2019
In the original version of this chapter, a wrong project number was stated in the Acknowledgements Section. This has now been corrected.
References
Liu, S.F., Cai, H., Yang, Y.J.: Advance in grey incidence analysis modelling. Syst. Eng. Theory Pract. 33(8), 2041–2046 (2013)
Liu, Z., Dang, Y.G., Zhou, W.J.: New grey nearness incidence model and its extension. Control. Decis. 29(6), 1071–1075 (2014)
Chen, Y.M., Zhang, M.: Cubic spline based grey absolute relational grade model. Syst. Eng. Theory Pract. 35(5), 1304–1310 (2015)
Jiang, S.Q., Liu, S.F., Liu, Z.X.: Grey incidence decision making model based on area. Control Decis. 30(4), 685–690 (2015)
Zhang, M., He, J.: Vector analysis on the fault-tolerant abilities of combined analog circuit systems. In: proceeding of International Congress on Image and Signal Processing, Biomedical Engineering and Informatics, pp. 2020–2025 (2017)
Chang, H., He, J.: A novel fault-tolerance design model for automatic synthesis of circuit robust to unknown fault. In: Proceeding of Conference Anthology, pp. 1–6. IEEE (2014)
Chang, H., He, J.: Swarm intelligence: making differences in analogue circuits structure for fault-tolerance. Int. J. Comput. Appl. Technol. 46(3), 210–219 (2013)
Zheng, Y., He, J.: Learning the distance between circuit structures for fault tolerance of redundant system. In: proceeding of Seventh International Symposium on Computational Intelligence and Design, pp. 207–211 (2015)
Chen, Z., Ni, M.: Reliability and security analysis of triple-module redundancy system. Comput. Eng. 38(14), 239–241 (2012)
Gao, G.J., Wang, Y.R., Yao, R.: Research on redundancy and tolerance of system with different structures. Transducer Microsyst. Technol. 26(10), 25–28 (2007)
Shi, W., Yuan, L., Xie, S.J.: Research on selective redundancy of evolved circuits using negative correlation. Microelectron Comput. 30(6), 71–74 (2013)
Wu, H.C., Wang, J.Z., Liu, C.C.: Research of circuit evolution design based on adaptive HereBoy algorithm. J. Hebei Univ. Sci. Technol. 36(3), 293–299 (2015)
Liu, M., He, J.: An evolutionary negative-correlation framework for robust analog-circuit design under uncertain faults. IEEE Trans. Evol. Comput. 17(5), 640–665 (2013)
Wu, H.C., Wang, J.Z., Zhou, W.Z.: Redundancy fault-tolerant circuit design based on feature map clustering and heterogeneous selection strategy. High Volt. Eng. 43(4), 1362–1369 (2017)
Zhang, J.B., Cai, J.Y., Meng, Y.F.: A design technology of fault tolerance circuit systems facing complex electromagnetic environments. J. Xi’an Jiaotong Univ. 51(2), 53–59 (2017)
Acknowledgments
This work was partly supported by the National Key R&D Program of China (No. 2017YFB0202302), the State Key Program of National Natural Science Foundation of China (No. 91530324).
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Wu, H., Yu, J., Wang, Y., Wang, X. (2018). Design of Heterogeneous Evaluation Method for Redundant Circuits. In: Qiu, M. (eds) Smart Computing and Communication. SmartCom 2018. Lecture Notes in Computer Science(), vol 11344. Springer, Cham. https://doi.org/10.1007/978-3-030-05755-8_40
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DOI: https://doi.org/10.1007/978-3-030-05755-8_40
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