Skip to main content
SpringerLink
Log in

Microprocessor Testing

  • Chapter
  • First Online:
Radiation Effects on Integrated Circuits and Systems for Space Applications

Abstract

Traditionally, satellites use radiation-hardened microprocessors for on-orbit computation. For many satellites commercial microprocessors could provide smaller, faster, and less power consuming options for on-orbit processing, as long as the mission can tolerate the increased risk. Unfortunately, most commercial microprocessors are not qualified for space usage, and it is up to the organization to determine good candidate parts and qualify them for for space. The qualification process includes testing the microprocessor for single-event effects that can disrupt the computation through silent data corruption and crashes. In this chapter, the fault models for how single-event effects affect computation are introduced so that radiation testers can determine what needs to be tested. Once the test goals are determined, different test protocols and designs are presented as options for testing a variety of microprocessor sub-systems. Currently, there are a number of issues with testing microprocessors, including programming languages, compilers/interpreters, algorithm design, operating systems, and fault injection. These topics are covered in the later part of the chapter.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. J.L. Hennessy, D.A. Patterson, Computer Architecture: A Quantitative Approach, 6th edn. (Morgan Kaufmann, Waltham, MA, 2017)

    Google Scholar 

  2. J. Emer, K. Asanovic, Arvind. Computer System Architecture, 2005. https://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-823-computer-system-architecture-fall-2005/

  3. Inductiveload, “Pipline MIPs,” (ed.) Wikimedia, 2009, pp. The stage-by-stage architecture of a MIPS microprocessor with a pipeline. Although the memory is shown twice for clarity of the pipeline, MIPS architectures have only one memory bank (i.e. von Neumann architecture)

    Google Scholar 

  4. H. Quinn, T. Fairbanks, J.L. Tripp, A. Manuzzato, The reliability of software algorithms and software-based mitigation techniques in digital signal processors, in Presented at the NSREC, 2013

    Google Scholar 

  5. J. Azambuja, F. Sousa, L. Rosa, F. Kastensmidt, The limitations of software signature and basic block sizing in soft error fault coverage, in Presented at the 11th Latin America Test Workshop (LATW), 2010

    Google Scholar 

  6. G. Torres, Inside Pentium 4 Architecture, 2005. http://www.hardwaresecrets.com/inside-pentium-4-architecture/2/

  7. md-rezaur-rahman, Intel® Xeon Phi™ Core Micro-architecture, 2013. https://software.intel.com/en-us/articles/intel-xeon-phi-core-micro-architecture

  8. C.J. Wells, The Central Processing Unit (CPU), 2009. https://www.technologyuk.net/computing/computer-systems/cpu.shtml

  9. F. Irom, Guideline for Ground Radiation Testing of Microprocessors in the Space Radiation Environment. JPL, 2008. https://trs.jpl.nasa.gov/handle/2014/40790

  10. S. M. Guertin, B. Wie, M.K. Plante, A. Berkley, L.S. Walling, M. Cabanas-Holmen, SEE test results for maestro microprocessor, in RADECs, 2012

    Google Scholar 

  11. H. Quinn, T. Fairbanks, J.L. Tripp, G. Duran, B. Lopez, Single-event effects in low-cost, low-power microprocessors, in NSREC, 2014

    Google Scholar 

  12. H. Quinn, Challenges in testing complex systems. IEEE Trans. Nucl. Sci. 61, 766–786 (2014)

    Article  Google Scholar 

  13. P. Rech, T.D. Fairbanks, H.M. Quinn, L. Carro, Threads distribution effects on graphics processing units neutron sensitivity. IEEE Trans. Nucl. Sci. 60, 4220–4225 (2013)

    Article  Google Scholar 

  14. C. Lunardi, H. Quinn, L. Monroe, D. Oliveira, P. Navaux, P. Rech, Experimental and analytical analysis of sorting algorithms error criticality for HPC and large servers applications. IEEE Trans. Nucl. Sci. 64, 2169–2178 (2017)

    Google Scholar 

  15. F.M. Lins, L.A. Tambara, F.L. Kastensmidt, P. Rech, Register file criticality and compiler optimization effects on embedded microprocessor reliability. IEEE Trans. Nucl. Sci. 64, 2179–2187 (2017)

    Google Scholar 

  16. M. Wirthlin, private communication, 2016.

    Google Scholar 

  17. Mantevo Project, 2018. https://mantevo.org/

  18. C. Hafer et al., LEON 3FT processor radiation effects data, in Presented at the IEEE Radiation Effects Data Workshop, Quebec City, QC, 2009

    Google Scholar 

  19. D.A.G. de Oliveira, L.L. Pilla, T. Santini, P. Rech, Evaluation and mitigation of radiation-induced soft errors in graphics processing units. IEEE Trans. Comput. 65, 791–804 (2016)

    Article  MathSciNet  Google Scholar 

  20. M. Wirthlin, D. Lee, G. Swift, H. Quinn, A method and case study on identifying physically adjacent multiple-cell upsets using 28-nm, interleaved and SECDED-protected arrays. IEEE Trans. Nucl. Sci. 61, 3080–3087 (2014)

    Article  Google Scholar 

  21. H. Quinn. Microcontroller Benchmark Codes. https://github.com/losalamos/benchmark_codes

  22. H. Quinn, Z. Baker, T. Fairbanks, J.L. Tripp, G. Duran, Robust duplication with comparison methods in microcontrollers. IEEE Trans. Nucl. Sci. 64, 338–345 (2017)

    Article  Google Scholar 

  23. L.D. Edmonds, Analysis of Single-Event Upset Rates in Triple-Modular Redundancy Devices, JPL, 2009. https://trs.jpl.nasa.gov/handle/2014/41123

  24. D.M. Hiemstra, A. Baril, Single event upset characterization of the Pentium(R) MMX and Celeron(R) microprocessors using proton irradiation, in Presented at the Radiation Effects Data Workshop, 2000

    Google Scholar 

  25. H. Wang, Q. Chen, L. Chen, D.M. Hiemstra, V. Kirischian, Single event upset characterization of the Tegra K1 Mobile processor using proton irradiation, in Presented at the NSREC, 2017

    Google Scholar 

  26. H. Quinn et al., Using benchmarks for radiation testing of microprocessors and FPGAs. IEEE Trans. Nucl. Sci. 62, 2547–2554 (2015)

    Article  Google Scholar 

  27. Politecnico di Torino ITC’99 benchkmarks. http://www.cad.polito.it/tools/itc99.html

  28. T. Ooura, Ooura’s Mathematical Software Packages. http://www.kurims.kyoto-u.ac.jp/~ooura/

  29. Mitigation Working Group, reliability.lanl.gov

  30. S.S. Mukherjee, C. Weaver, J. Emer, S.K. Reinhardt, T. Austin, A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor, in Presented at the International Symposium Microarchitecture (MICRO-36), 2003

    Google Scholar 

  31. V. Sridharan, D.R. Kaeli, Eliminating microarchitectural dependency from architectural vulnerability, in Presented at the 15th International Symposium High-Performance Computer Architecture (HPCA-15), 2009

    Google Scholar 

  32. R. Velazco, S. Rezgui, R. Ecoffet, Predicting error rate for microprocessor-based digital architectures through CEU (code emulating upsets) injection. IEEE Trans. Nucl. Sci. 47, 2405–2411 (2000)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Space Data Systems and Sciences, Los Alamos National Laboratory, Los Alamos, NM, 87545, USA

    Heather Quinn

Authors
  1. Heather Quinn
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Heather Quinn .

Editor information

Editors and Affiliations

  1. Centre Nationale Recherche Scientifique (CNRS), Grenoble, France

    Raoul Velazco

  2. United States Naval Research Laboratory, Washington, DC, USA

    Dale McMorrow

  3. Spectrum Aerospace Group, Munich, Germany

    Jaime Estela

Rights and permissions

Reprints and permissions

Copyright information

© 2019 Springer Nature Switzerland AG

About this chapter

Check for updates. Verify currency and authenticity via CrossMark

Cite this chapter

Quinn, H. (2019). Microprocessor Testing. In: Velazco, R., McMorrow, D., Estela, J. (eds) Radiation Effects on Integrated Circuits and Systems for Space Applications. Springer, Cham. https://doi.org/10.1007/978-3-030-04660-6_5

Download citation

  • DOI: https://doi.org/10.1007/978-3-030-04660-6_5

  • Published:

  • Publisher Name: Springer, Cham

  • Print ISBN: 978-3-030-04659-0

  • Online ISBN: 978-3-030-04660-6

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation