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Abstract

The effects produced by radiation on integrated circuits can be classified into Single Event Effects (SEE) related to transient problems and Total Ionization Dose (TID) effects that arise due to the long exposure time to ionizing radiation. The mitigation of these effects on integrated circuits can be done in three ways: Manufacturing Process Level, Architectural Level (redundancy) and Layout Level. The work presented here deals with the third way of mitigation, that is, the cell library design of radiation tolerant integrated circuits. Designed and manufactured in silicon on 150 nm technology, the SMDH-RH library is based on the use of guard rings and the application of closed geometry techniques (ELT—Enclosed Layout Transistor). The library includes simple and complex digital logic gates. It was tested in space as payload of a nanosatellite (NanosatC-Br1), launched in space in 2014 and still in activity, being approved its operation and functionality.

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References

  1. J. Puig-Suari, C. Turner, W. Ahlgren, Development of the standard CubeSat deployer and a CubeSat class PicoSatellite, in 2001 IEEE Aerospace Conference Proceedings (Cat. No.01TH8542), Big Sky, MT, USA, 2001, vol. 1, pp. 1/347–1/353

    Google Scholar 

  2. European Space Agency (ESA), Space Product Assurance—Techniques for radiation effects mitigation in ASICs and FPGAs, European Cooperation for Space Standardization, 2012

    Google Scholar 

  3. J.J.S. Noval, L. Medeiros, J.B.S. Martins, N.J. Schuch, O. DurÐo, R. Machado. Design considerations for Radiation Hardened ASIC used as technological payload in NANOSATC-BR1, in II Latin American IAA CubeSat Workshop, 2016, Florianopolis. Conference Proceedings 2nd IAA, 2016

    Google Scholar 

  4. L. Medeiros, C. Zaffari, J. Noval, L. Teixeira, J.B.S. Martins, Using the NanoSatC-Br1 to evaluate the effects of space radiation incidence on a radiation hardened ASIC, in 1st IAA Latin American Cubesat IAA Workshop , Florianopolis, 2015

    Google Scholar 

  5. R. Sharma, Characterization and modeling of digital circuits, 2nd edn. (Independently Published, San Francisco, 2015)

    Google Scholar 

  6. J.R. Schwank et al., Radiation effects in MOS oxides. IEEE Trans. Nucl. Sci. 55 (4), 1833–1853 (2008)

    Article  Google Scholar 

  7. S.E. Ivan, Modeling of total ionizing dose effects in advanced complementary metal-oxide-semiconductor technologies, Doctoral dissertation, Arizona State University, May 2011

    Google Scholar 

  8. N.S. Saks, M.G. Ancona, J.A. Modolo, Radiation Effects in MOS capacitors with very thin oxides at 80¯K. IEEE Trans. Nucl. Sci. 31 (6), 1249 (1984)

    Article  Google Scholar 

  9. R.C. Jaeger, Thermal oxidation of silicon, in Introduction to Microelectronic Fabrication, (Prentice Hall, Upper Saddle River, 2001)

    Google Scholar 

  10. G. Anelli et al., Total dose behaviour of submicron and deep submicron CMOS technologies, Workshop on Electronics for LHC Experiments, 1997, p. 139

    Google Scholar 

  11. A. Giraldo, A. Paccagnella, A. Minzoni, Aspect ratio calculation in nchannel MOSFETs with a gate-enclosed layout. Solid State Electron. 44 (6), 981 (2000)

    Article  Google Scholar 

  12. R.L. Shuler, A. Balasubramanian, B. Narasimham, B.L. Bhuva, P.M. O’ Neill, C. Kouba, The effectiveness of TAG or guard-gates in SET suppression using delay and dual-rail configurations at 0.35 μm. IEEE Trans. Nucl. Sci. 53 (6), 3428–3431 (2006)

    Article  Google Scholar 

  13. Q. Zhou, K. Mohanram, Cost-effective radiation hardening technique for combinational logic, in IEEE/ACM International Conference on Computer Aided Design, ICCAD-2004 , (San Jose, CA, USA, 2004), pp. 100–106

    Google Scholar 

  14. T. Calin, M. Nicolaidis, R. Velazco, Upset Hardened Memory Design for Submicron CMOS Technology. IEEE Transactions on Nuclear Science 43 (6), 2874–2878 (December 1996)

    Article  Google Scholar 

  15. B.J. LaMeres, S. Harkness, M. Handley et al., RadSat—Radiation tolerant SmallSat computer system, 29th Annual AIAA/USU Conference on Small Satellites , 2015

    Google Scholar 

  16. European Space Agency (ESA), Spacecraft Discrete Interfaces, European Cooperation for Space Standardization, 2012

    Google Scholar 

  17. European Space Agency (ESA), Total Dose Irradiation Steady-State Test Method, ESA/SCC Basic Specification No. 22900, 2016.

    Google Scholar 

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Correspondence to João Baptista S. Martins .

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Martins, J.B.S., Noval, J.J.S. (2019). Development of a Hardened 150 nm Standard Cell Library. In: Velazco, R., McMorrow, D., Estela, J. (eds) Radiation Effects on Integrated Circuits and Systems for Space Applications. Springer, Cham. https://doi.org/10.1007/978-3-030-04660-6_11

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  • DOI: https://doi.org/10.1007/978-3-030-04660-6_11

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