Abstract
In this paper, we have proposed a novel VLSI-oriented parallel algorithm for quaternion-based rotation in 3D space. The advantage of our algorithm is a reduction the number of multiplications through replacing part of them by less costly squarings. The algorithm uses Logan’s trick, which proposes to replace the calculation of the product of two numbers on summing the squares via the Binomial theorem. Replacing digital multipliers by squaring units implies reducing power consumption as well as decreases hardware circuit complexity.
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Cariow, A., Cariowa, G. (2019). Hardware-Efficient Algorithm for 3D Spatial Rotation. In: Pejaś, J., El Fray, I., Hyla, T., Kacprzyk, J. (eds) Advances in Soft and Hard Computing. ACS 2018. Advances in Intelligent Systems and Computing, vol 889. Springer, Cham. https://doi.org/10.1007/978-3-030-03314-9_33
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DOI: https://doi.org/10.1007/978-3-030-03314-9_33
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