A Hybrid Approach to Fault Detection in One Round of PP-1 Cipher

Abstract

Deliberate injection of faults into cryptographic devices is an effective cryptanalysis technique against symmetric and asymmetric encryption algorithms. In this paper we describe concurrent error detection (CED) approach against such attacks in substitution-permutation network symmetric block ciphers on the example of PP-1 cipher. The specific objective of the design is to develop a method suitable for compact ASIC implementations targeted to embedded systems such as smart cards, cell phones, PDAs, and other mobile devices, such that the system is resistant to fault attacks. To provide the error detection it is proposed to adopt a hybrid approach consisting of multiple parity bits in combination with time redundancy. Taking such an approach gives a better ability to detect faults than simple parity codes. The proposed hybrid CED scheme is aimed at area-critical embedded applications, and achieves effective detection for single faults and most multiple faults. The system can detect the errors shortly after the faults are induced because the detection latency is only the output delay of each operation.