ATPG Binning and SAT-Based Approach to Hardware Trojan Detection for Safety-Critical Systems

Abstract

Combating threats and attacks imposed by Hardware Trojans that are stealthily inserted in hardware systems, has surfaced as a challenging problem in recent times. Such threats degrade the reliability and endanger security of the system. Due to scalability issues, Trojan detection remains an extremely difficult problem, especially, when the circuit size is large and Trojan sizes are small. Hardware Trojan is surreptitiously inserted into the design by selecting a few circuit nodes, where rare logic value occurs. This makes their detection probability negligibly small, thereby rendering the arrival of an input combination activating the same, an extremely rare event. Since the number of such Trojans may be exponentially large in terms of such rare nodes, almost all state-of-art techniques suffer from scalability bottlenecks and coverage issues, while generating test vectors. In this work, we propose a systematic approach to sampling in order to lessen the search space, yet preserving the diversity of population. We use binning of trigger-population based on Automatic Test Pattern Generation (ATPG), and invoke Boolean Satisfiability (SAT) solvers to generate test vectors with high Trojan coverage. Simulation results demonstrate the effectiveness and superiority of our method with respect to prior work in terms of Trojan coverage and the cardinality of the test set.