Abstract
Chip manufactures introduce redundancy at various levels of CPU design to guarantee correct operation even for worst-case combinations of non-idealities in process variation and system operation conditions. This redundancy is implemented partly in the form of voltage/frequency margins. However, for a wide range of real-world execution scenarios, these margins are excessive and translate to increased power and energy consumption. Among the various factors that affect the degree to which these margins are actually needed to avoid errors during program execution, the impact of compiler and source code optimizations has not been explored yet. In this work, we study the effect of such optimizations on the frequency margins and the energy efficiency of applications in the ARM Cortex-A53 processor.
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References
Ashraf, R.A., Gioiosa, R., Kestor, G., DeMara, R.F.: Exploring the effect of compiler optimizations on the reliability of HPC applications. In: Processing on the International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp. 1274–1283 (2017)
Bacha, A., Teodorescu, R.: Using ECC feedback to guide voltage speculation in low-voltage processors. In: Proceedings of 47th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 306–318, December 2014. https://doi.org/10.1109/MICRO.2014.54
Bacha, A., Teodorescu, R.: Dynamic reduction of voltage margins by leveraging on-chip ECC in itanium II processors. SIGARCH Comput. Archit. News 41(3), 297–307 (2013). https://doi.org/10.1145/2508148.2485948
Bergman, K., Borkar, S., Campbell, D., Carlson, W., Dally, W., et al.: Exascale computing study: technology challenges in achieving exascale systems. Technical report, DARPA IPT (2008)
Bienia, C., Kumar, S., Singh, J.P., Li, K.: The PARSEC benchmark suite: characterization and architectural implications. In: Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 72–81. ACM (2008)
Das, S., et al.: A self-tuning DVS processor using delay-error detection and correction. IEEE J. Solid State Circuits 41(4), 792–804 (2006)
Henning, J.L.: SPEC CPU2006 benchmark descriptions. SIGARCH Comput. Archit. News 34(4), 1–17 (2006). https://doi.org/10.1145/1186736.1186737. ISSN 0163-5964
Leng, J., Buyuktosunoglu, A., Bertran, R., Bose, P., Reddi, V.J.: Safe limits on voltage reduction efficiency in GPUs: a direct measurement approach. In: Proceedings of the 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 294–307 (2015). https://doi.org/10.1145/2830772.2830811
Measurement Computing: USB 205 Data Acquisition USB Device
Papadimitriou, G., Kaliorakis, M., Chatzidimitriou, A., Gizopoulos, D., Lawthers, P., Das, S.: Harnessing voltage margins for energy efficiency in multicore CPUs. In: Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 503–516 (2017)
Papadimitriou, G., Kaliorakis, M., Chatzidimitriou, A., Magdalinos, C., Gi-zopoulos, D.: Voltage margins identification on commercial x86-64 multi-core microprocessors. In: Proceedings of the 23rd International Symposium on On-Line Testing and Robust System Design (IOLTS), pp. 51–56 (2017). https://doi.org/10.1109/IOLTS.2017.8046198
rsta2: Circle: a c++ bare metal programming environment for the Raspberry Pi. https://github.com/rsta2/circle
Yazdanbakhsh, A., Mahajan, D., Lotfi-Kamran, P., Esmaeilzadeh, H.: AXBENCH: a multi-platform benchmark suite for approximate computing. IEEE Des. Test 34, 60–68 (2016)
Zu, Y., Lefurgy, C.R., Leng, J., Halpern, M., Floyd, M.S., Reddi, V.J.: Adaptive guardband scheduling to improve system-level efficiency of the POWER7. In: Proceedings of the 48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 308–321 (2015)
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Parasyris, K., Bellas, N., Antonopoulos, C.D., Lalis, S. (2018). Exploring the Effects of Code Optimizations on CPU Frequency Margins. In: Yokota, R., Weiland, M., Shalf, J., Alam, S. (eds) High Performance Computing. ISC High Performance 2018. Lecture Notes in Computer Science(), vol 11203. Springer, Cham. https://doi.org/10.1007/978-3-030-02465-9_42
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DOI: https://doi.org/10.1007/978-3-030-02465-9_42
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