Memory Circuits and Systems

Abstract

Basic serial and parallel bus structures and different forms of data transfer between a bus master and a slave were explained in Chap. 4. Regardless of the bus architecture, the bus master is defined as the logic block that initiates the data transfer while the slave is defined as the device that can only listen and exchange data with the master on demand.

Review Questions

• 1.

  An SDRAM is composed of two16-bit wide banks, bank 0 and bank 1, as shown below.

The truth table below defines precharge, activate and read cycles.

Each 16-bit SDRAM address is composed of two parts: the most significant byte corresponds to the row address , and the least significant byte to the column address as shown below.

Address = {Row Address , Column Address }

The wait period between the precharge and activate commands is one clock cycle. Similarly, the wait period between the activate and read commands is also one cycle. The read burst from the specified address starts after a latency of two cycles. The waiting period between the last data packet and the next precharge command is also one cycle if the read repeats from the same bank.

• (a) Show two read sequences in sequential addressing mode from Bank 0. Each burst contains four data packets: the first burst from address 0xAB03 and the next from address 0xAB07.

• (b) Show the two read sequences in sequential addressing mode from different banks with no delay in between. Each burst contains four data packets: the first burst from Bank 0 with the starting address 0xAB03 and the next from Bank 1 with the address 0xCD06.

• 2.

  A Flash memory is composed of two byte-addressable sectors. It has an eight-bit bidirectional I/O port for reading and writing data, and a 16-bit unidirectional address port. The upper eight bits of the address field are allocated for the sector address and the lower eight bits for the program address. The three active-low inputs, $\overline{\text{EN}}$, $\overline{\text{RE}}$ and $\overline{\text{WE}}$, control the Flash memory according to the following chart:

The initial data contents in this memory are shown below:

The Flash command chart is as follows:

In this diagram, the sector protect is a three-cycle sequence where the sector protect code, 0x01, is provided in the third cycle along with the sector address.

Both the fast write and the read processes are initially three cycles. However, once the process starts, additional reads or writes are reduced to two-cycle operations as shown in the flow chart below. According to this chart, for each additional data to be read or written, the command code must be employed in the second cycle, and the address/data combination in the third cycle.

The flow chart for fast write and read is as follows:

• (a) Protect sector 1. Show the timing diagram with control inputs, address and data.

• (b) Fast write to sector 0 with four bytes of data, 0x11, 0x22, 0x33, 0x44, starting from address 0x04 and incrementing the address to write each byte of data. Show the timing diagram with control inputs, address and data.

• (c) Read four bytes from sector 0 at addresses 0x00, 0x02, 0x04 and 0x06. Show the timing diagram with control inputs, address and data.

• 3.

  Two reads can be accomplished from a 16-bit wide SDRAM by a single CPU instruction.

SDRAM is organized by four banks with data shown below.

Each SDRAM address is composed of an eight-bit wide row address , RA[7:0], and an eight-bit wide column address , CA[7:0], as in the following format:

SDRAM Address = {RA[7:0], CA[7:0]} where the row address occupies higher bits.

To control SDRAM , the following controls are available:

The wait period between the precharge and activate commands is one clock cycle long. Similarly, the wait period between the activate and read commands is also one clock cycle. The precharge command for the next read operation can be issued one clock cycle after the last data is read out from SDRAM . BS[1:0] = 0 selects Bank0, BS[1:0] = 1 selects Bank1, BS[1:0] = 2 selects Bank2, and BS[1:0] = 3 selects Bank3 in the timing diagrams.

• (a) Assuming that the mode register is pre-programmed with sequential mode addressing , a burst length of four and a CAS latency of two, construct a timing diagram to show the two reads from SDRAM addresses, 0xAA00 and 0xAA04. Start from the precharge cycle to accomplish each read.

• (b) With the same mode register contents in part (a), construct a timing diagram such that the two reads from the SDRAM addresses, 0xAA00 and 0xBB02, take place in the shortest possible time. Again start from the precharge cycle to accomplish each read. In this part, the bus master can extend the wait period more than one clock cycle between the precharge, activate and read commands in such a way that no two commands overlap with each other.

• (c) With the same mode register contents in part (a), accomplish one read from the SDRAM address 0xCC00 with a burst length of two, and one read from the SDRAM address 0xDD02 with a burst length of eight. Start from the precharge cycle to accomplish each read.

• 4.

  Subsequent write and read operations are performed on an SDRAM that consists of two banks. Both banks have eight-bit wide I/O data ports .

The first SDRAM operation is a write operation that writes 0x11 to a starting address of 0xAB in bank 0. This is followed by writing data values, 0xEE, 0x00 and 0xFF, to bank 0 in sequential mode.

The read operation takes place from bank 1 without any interruption. This means the first read data is delivered to the data bus immediately after the last write data, 0xFF. The first read address is defined as 0x12. Four data packets are read from this starting address in sequential mode with a latency of two cycles.

Both write and read operations require t_PRE = t_CAS = 1 cycle.

Construct a timing diagram with control, address and data values to achieve these two consecutive operations. Assume all initial data values in Bank 0 are 0x00. Make sure to mark each precharge, activate, write and read cycle on the timing diagram. Indicate where latency happens.

• 5.

  An E²PROM memory is organized in four sectors. There are eight columns in each sector but no pages. The existing data in this memory is shown below.

The command truth table is given below.

The memory has five control pins:

$\overline{\text{EN}}$ is an active-low signal that activates the sector

AE is an active-high signal that accepts address

CE is an active-high signal that enables command function

$\overline{\text{WE}}$ is an active-low signal that enables write

$\overline{\text{RE}}$ is an active-low signal that enables read

Writing to the memory takes place at the rising edge of $\overline{\text{WE}}$. At the falling edge of $\overline{\text{RE}}$, reads take place from the memory. The sequence of write starts with the command function followed by an address and then data. A read sequence follows a similar fashion: it starts with the read command, then an address and data. Assume all AE, $\overline{\text{WE}}$ and $\overline{\text{RE}}$ set-up times are 0 s. The setup and hold times for command, address and data are all different from 0 s. It takes t_WRITE to transfer data from the buffer to the memory core.

• (a) Draw a timing diagram to read data from column address  = 0 and sector address = 3.

• (b) Draw a timing diagram to write 0xA, 0xB, 0xC, 0xD, 0xE, 0xF, 0x7, 0x6 starting from the column address  = 2 and the sector address = 2 in the following manner: the first data, 0xA, to column address 2; the second data, 0xB, to address 0x3 and so forth. Draw the contents of the memory after the write sequence is complete.

• 6.

  A Flash memory has an eight-bit address, and all reads and writes are achieved on an eight-bit bidirectional data bus. The Flash memory write sequence contains a preamble, a write command, and an address and data combination as shown in the flow chart below.

Once the write command is issued, address and data are generated continuously until the last write. The sequence ends with the same preamble that started the write.

In the read sequence, the bus master starts fetching data once the preamble and read command are issued. The sequence has the same exit preamble as shown below.

START and DONE do not have any significance in timing diagrams other than that they indicate the start and the end of the sequence, respectively.

The preamble, write and read commands are issued with hexadecimal values shown in the truth table below.

The state of the Flash memory before any read or write operation is shown below. The leftmost column in this figure shows the Flash memory address in hexadecimal.

The bus master produces three data transmissions for the Flash memory . In the first transmission, four data packets below are written into the Flash memory .

In the second transmission, the bus master reads two data packets from the following addresses below.

In the third transmission, the bus master reads two more data packets from the following addresses.

Construct a timing diagram with Address, $\overline{\text{WE}}$, $\overline{\text{RE}}$ and Data values. Note that the Flash memory requires a hold period which coincides with the high phase of $\overline{\text{EN}}$ signal. However, in the low phase, when the Flash memory is active, the device either writes or reads depending on the value of $\overline{\text{WE}}$ and $\overline{\text{RE}}$ signals, respectively.

• 7.

  A serial on-chip SPI bus described in Chap. 4 is used to program an SDRAM register file that consists of five registers (see the SDRAM bus interface architecture).

Assume that each register in the register file has an eight-bit long address. Data in each register is also assumed to be eight bits long.

Wait register receives the number of clock periods which is equivalent to t_WAIT, Latency register to t_LAT, Burst register to t_BURST, CAS register to t_CAS, and Precharge register to t_PRE.

The SPI bus uses its SDI terminal and sends out an eight-bit address (starting with the most significant bit) followed by an eight-bit data (again starting with the most significant bit) at the positive edge of SCK until all five registers are programmed while $\overline{\text{SS}}$ is at logic 0. Once the programming is finished, $\overline{\text{SS}}$ node is pulled to logic 1.

Design the interface between the SPI bus and the register file. Make sure to show each I\/O port of the SPI bus (such as SCK, SDI, $\overline{\text{SS}}$ etc.), the internal address, data and control signals of the interface on the timing diagram. The functionality of the interface must be identical between the timing diagram and the data-path.

Start building the timing diagram that includes only the address and the data. Then form the corresponding data-path that matches the timing diagram. Increase the complexity of the design by including the control signals in the timing diagram, governing the flow of data. Lastly, draw the state diagram of the Moore type controller for the interface.

Projects

• 1. Implement and verify the SRAM bus interface unit with the unidirectional bus designed in Chap. 4. Use Verilog as the hardware design language for the module implementation and functional verification.

• 2. Implement and verify the SDRAM bus interface unit with the unidirectional bus designed in Chap. 4. Use Verilog as the hardware design language for the module implementation and functional verification. Produce the hardware to program the SDRAM register file. Assume a serial bus such as SPI or I²C to distribute the program data to the registers.

• 3. Implement and verify the I²C fast write interface in the first design example in this chapter using Verilog.

• 4. Implement and verify the I²C read interface in the second design example using Verilog.

• 5. Combine the read and the fast write interfaces into a single unit. Design and verify the complete interface using Verilog.

Note that for projects 3 through 5, write a behavioral Verilog code that mimics the bus master in order to send data on the I²C bus.