Abstract
The Verilog-2001 Standard includes a number of enhancements that are targeted at simplifying designs, improving designs and reducing design errors.
This paper details important enhancements that were added to the Verilog-2001 Standard that are intended to simplify behavioral modeling and to improve synthesis accuracy and efficiency. Information is provided to explain the reasons behind the Verilog-2001 Standard enhancement implementations
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References
IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language, IEEE Std PI3641D5
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Don Mills and Clifford E. Cummings, “RTL Coding Styles That Yield Simulation and Synthesis Mismatches,” SNUG 99 (Synopsys Users Group San Jose, CA, 1999) Proceedings, section-TA2 (Is paper), March 1999.
Clifford E. Cummings, “full_case parallel_case”, the Evil Twins of Verilog Synthesis,’ SNUG 99 Boston (Synopsys Users Group Boston, MA, 1999) Proceedings, section-FA1 (2nd paper), October 1999.
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© 2002 Springer Science+Business Media New York
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Cummings, C.E. (2002). Verilog-2001 Behavioral and Synthesis Enhancements. In: Mignotte, A., Villar, E., Horobin, L. (eds) System on Chip Design Languages. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-6674-5_2
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DOI: https://doi.org/10.1007/978-1-4757-6674-5_2
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-5281-3
Online ISBN: 978-1-4757-6674-5
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