Abstract
Measurements are presented of the effect that line coupling produces on the transition delay of a signal when a signal commutes simultaneously in an adjacent line. A specific test circuit for the measurements has been used, implemented with an ASIC in 1.2 µm technology.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
MoIl F. and Rubio A., Spurious Signals in Digital CMOS VLSI Circuits A propagation Analysis”, IEEE Transactions on Circuits and Systems-fl, 39(10). 1992.
Brews MA. and Gupta S.K., Process Aggravated Noise (PAN) New Validation and Test Problems”, IEEE International Test Conference, 1996.
linger S,H. and Tan Cl., “Clocking Schemes for High-Speed Digital Systems”, IEEE Transactions on Computers, C-35(lO), October 1986.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1998 Springer Science+Business Media New York
About this chapter
Cite this chapter
Moll, F., Roca, M., Rubio, A., Sicard, E. (1998). Analysis and Measurement of Crosstalk-Induced Delay Errors in Integrated Circuits. In: Grabinski, H., Nordholz, P. (eds) Signal Propagation on Interconnects. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-6512-0_12
Download citation
DOI: https://doi.org/10.1007/978-1-4757-6512-0_12
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-5059-8
Online ISBN: 978-1-4757-6512-0
eBook Packages: Springer Book Archive