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Testing Defects in Programmable Logic Circuits

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Defect Oriented Testing for CMOS Analog and Digital Circuits

Part of the book series: Frontiers in Electronic Testing ((FRET,volume 10))

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Abstract

Recent resurgence of programmable logic devices (PLDs) ushers a new era in digital system design. Modern PLD architectures offer flexibility of logic implementation. However, the same flexibility results in enormous test complexity. In this chapter, a brief review of testable PLD architecture is presented and methodologies for testing defects are outlined.

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Authors and Affiliations

  1. Philips Research, The Netherlands

    Manoj Sachdev

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  1. Manoj Sachdev
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© 1999 Springer Science+Business Media Dordrecht

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Sachdev, M. (1999). Testing Defects in Programmable Logic Circuits. In: Defect Oriented Testing for CMOS Analog and Digital Circuits. Frontiers in Electronic Testing, vol 10. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-4926-7_6

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  • DOI: https://doi.org/10.1007/978-1-4757-4926-7_6

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4757-4928-1

  • Online ISBN: 978-1-4757-4926-7

  • eBook Packages: Springer Book Archive

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