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Defect Oriented Testing for CMOS Analog and Digital Circuits pp 133–204Cite as

Defect Oriented RAM Testing and Current Testable RAMs

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Part of the book series: Frontiers in Electronic Testing ((FRET,volume 10))

Abstract

RAMs are integral building blocks of modern ICs and systems. As far as the testing is concerned, RAMs suffer from quantitative issues of digital testing along with the qualitative issues of analog testing. This chapter reviews the state of the art of defect oriented testing of RAMs and proposes a RAM test methodology using IDDQ and voltage based march tests. Bridging defects in a RAM matrix, including the gate oxide defects, are detected by four IDDQ measurements. The IDDQ test is then supplemented with voltage based march test to detect the defects (opens and data retention) not detectable by the IDDQ technique. The combined test methodology reduces the algorithmic test complexity substantially.

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Authors and Affiliations

  1. Philips Research, The Netherlands

    Manoj Sachdev

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  1. Manoj Sachdev
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© 1999 Springer Science+Business Media Dordrecht

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Sachdev, M. (1999). Defect Oriented RAM Testing and Current Testable RAMs. In: Defect Oriented Testing for CMOS Analog and Digital Circuits. Frontiers in Electronic Testing, vol 10. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-4926-7_5

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  • DOI: https://doi.org/10.1007/978-1-4757-4926-7_5

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4757-4928-1

  • Online ISBN: 978-1-4757-4926-7

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