Skip to main content

Abstract

Numerous studies have appeared which compare various packaging technologies [5.1–5.16]. These studies contain valuable information about the general applicability of one technology or material over another. Application specific tradeoff studies have also appeared, but are less prevalent than generic treatments [5.17–5.23]. These studies present tradeoff analyses for specific real modules.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. D. Balderes and M. White, “Packaging Effects on CPU Perfor- mance of Large Commercial Processors,” Proceedings of the 35th Electronic Components Conference, pp. 351–356, 1985.

    Google Scholar 

  2. H. B. Bakoglu and J. D. Meindl, “A System Level Circuit Model for Multi-and Single-Chip CPU’s,” Proceedings of the IEEE International Solid State Circuits Conference, pp. 308–309, 1987.

    Google Scholar 

  3. C. A. Neugebauer and R. O. Carlson, Comparison of Wafer Scale Integration with VLSI Packaging Approaches, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. CHMT-10, no. 2, pp. 184–189, June, 1987.

    Google Scholar 

  4. J. P. Krusius and W. E. Pence, “Analysis of Materials and Structure Tradeoffs in Thin and Thick Film Multi-Chip Packages,” Proceedings of the Electronic Components Conference, pp. 641–646, 1989.

    Google Scholar 

  5. V. K. Nagesh, D. Miller, and L. Moresco, “A Comparative Study of Interconnect Technologies,” Proceedings of the International Electronic Packaging Symposium (IEPS), pp. 433–443, 1989.

    Google Scholar 

  6. C. A. Neugebauer, “Materials for High-Density Electronic Packaging and Interconnections in the Higher Packaging Levels,” J. of Electronic Materials, vol. 18, no. 2, part 2, pp. 229–239, March, 1989.

    Google Scholar 

  7. ] R. Kaw, “Comparison of Chip Crossing Delay in Various Packaging Environments,” Proceedings of the International Conference on Computer Design pp. 233–236, 1989.

    Google Scholar 

  8. L. L. Moresco, “Electronic System Packaging: The Search for Manufacturing the Optimum in a Sea of Constraints,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 13, pp. 494–508, September, 1990.

    Google Scholar 

  9. ] R. Hannemann, “Interconnects and Packaging for Highly Integrated Systems,” Presented at SPIE International Conference on Advances in Interconnect and Packaging 1990.

    Google Scholar 

  10. J. P. Krusius, “System Interconnection of High Density Multi-Chip Modules,” Proceedings of the SPIE International Conference on Advances in Interconnects and Packaging, vol. 1390, pp. 261–270, 1990.

    Google Scholar 

  11. L. L. Moresco, “System Interconnect Issues for Sub-Nanosecond Signal Transmission,” Proceedings of the SPIE International Conference on Advances in Interconnects and Packaging, vol. 1390, pp. 202–213, 1990.

    Google Scholar 

  12. C. A. Neugebauer, R. A. Fillion, W. Daum, and M. Gdula, “The Single Chip Versus Multichip Packaging Option for Digital CMOS in the 1990’s,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Vol. 15, no. 5, pp. 915–921, October, 1992.

    Article  Google Scholar 

  13. G. Messner and W. Smit, “Equations for Selection of Cost-Efficient Interconnection Designs,” Proceedings of Electronic Component and Technology Conference, pp. 10–16, 1992.

    Google Scholar 

  14. L. W. Schaper, “Meeting System Requirements Through Technology Tradeoffs in Multi-Chip Modules,” Proceedings of the International Electronic Packaging Symposium (IEPS), pp. 25–33, 1990.

    Google Scholar 

  15. M. Terasawa and S. Minami, “A Comparison of Thin Film, Thick Film, and Co-Fired High Density Ceramic Multilayer with the Combined Technology: T and T HDCM (Thin Film and Thick Film High Density Ceramic Module),” International Journal for Hybrid Microelectronics, vol. 6, no. 1, pp. 607–615, October, 1983.

    MathSciNet  Google Scholar 

  16. A. Iqbal, M. Swaminathan, M. Nealon, and A. Omer, “Design Tradeoffs Among MCM-C, MCM-D and MCM-D/C Technologies,” Proceedings of the IEEE Multi-Chip Module Conference (MCMC), pp. 12–17, 1993.

    Google Scholar 

  17. P. A. Sandborn, “A Software Tool for Technology Tradeoff Evaluation in Multichip Packaging,” Proceedings of the International Electronics Manufacturing Technology Symposium, pp. 337–341, 1991.

    Google Scholar 

  18. M. M. Salatino and R. C. Braken, “Die and MCM Test Strategy: The Key to MCM Manufacturability,” Proceedings of the Eleventh International Electronics Manufacturing Technology Symposium, pp. 440–445, 1991.

    Google Scholar 

  19. M. M. Salatino and R. C. Bracken, “Assembly Choices in Multi-Chip Module Fabrication, The Harris Digital Drop Receiver DDR-1,” Proceedings of the 1st International Conference on Multichip Modules, pp. 74–82, 1992.

    Google Scholar 

  20. J. Shiao and D. Nguyen, “Performance Modeling of a Cache System with Three Technologies: Cyanate Ester PCB, Chip-on-Board, and Cu/PI MCM,” Proceedings of the IEEE Multichip Module Conference, pp. 134–137, 1992.

    Google Scholar 

  21. P. A. Sandborn, “Technology Application Tradeoff Studies in Multichip Systems,” Proceedings of the 1st International Conference on Multichip Modules, pp. 150–158, 1992.

    Google Scholar 

  22. P. A. Sandborn, H. Hashemi and L. Bal, “Design of MCMs for Insertion into Standard Surface Mount Packages,” Proceedings of the National Electronic Packaging and Production Conference (NEPCON-West), pp. 651–660, 1993.

    Google Scholar 

  23. S. Rao, B. Haskell, and I. Yee, “Trade-Off Analysis on Cost and Manufacturing Technology of an Electronic Product: Case Study,” Proceedings of the Second International Workshop on The Economics of Design, Test, and Manufacturing for Electronic Circuits and Systems, 1993.

    Google Scholar 

  24. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley Publishing Company, 1990.

    Google Scholar 

  25. D. W. Dobberpuhl, et al, “A 200-MHz 64-b Dual-Issue CMOS Microprocessor,” IEEE J. of Solid-State Circuits, vol. 27, no. 11, pp. 1555–1567, November, 1992.

    Article  Google Scholar 

  26. P. H. Dehkordi and D. W. Bouldin, “Design for Packagability: The Impact of Bonding Technology on the Size and Layout of VLSI Dies,” Proceedings of the IEEE Multichip Module Conference, pp. 153–159, 1993.

    Google Scholar 

  27. M. Abadir, A. Parikh, L. Bal, P. Sandborn, and C. Murphy, “High Level Test Economics Advisor (Hi-TEA),” Proceedings of the Economics of Design, Test, and Manufacturing Workshop, 1993.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Rights and permissions

Reprints and permissions

Copyright information

© 1994 Springer Science+Business Media New York

About this chapter

Cite this chapter

Sandborn, P.A., Moreno, H. (1994). Tradeoff Analyses for Multichip Systems. In: Conceptual Design of Multichip Modules and Systems. The Springer International Series in Engineering and Computer Science, vol 250. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-4841-3_5

Download citation

  • DOI: https://doi.org/10.1007/978-1-4757-4841-3_5

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-5137-3

  • Online ISBN: 978-1-4757-4841-3

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics