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Tradeoff Analysis

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Conceptual Design of Multichip Modules and Systems

Part of the book series: The Springer International Series in Engineering and Computer Science ((SECS,volume 250))

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Abstract

Tradeoff analysis is the process of comparing performance gains in one region of the design space with the associated performance losses in another. When simply enough systems are considered or the design constraints are strong enough, tradeoff analysis may lead to design optimization. However, in general, tradeoff analysis is performed at a “what if” level.

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References

  1. A. M. Dewey and S. W. Director, Principles of VLSI System Planning: A Framework for Conceptual Design, Kluwer Academic Publishers, 1990.

    Google Scholar 

  2. J. L. Sloan, Design and Packaging of Electronic Equipment, Van Nostrand Reinhold Company, 1985.

    Google Scholar 

  3. B.S. Landman and R.L. Russo, “On a Pin Versus Block Relationship for Partitions of Logic Graphs,” IEEE Transactions on Computers, vol. C-20, pp. 1469–1479, December, 1971.

    Google Scholar 

  4. W. Donath, “Equivalence of Memory to ‘Random Logic’,” IBM Journal of Research and Development, vol. 58, no. 5, pp. 401–407, September, 1974.

    Article  MathSciNet  Google Scholar 

  5. M. Feuer, “Connectivity of Random Logic,” IEEE Transactions on Computers, vol. C-31, pp. 29–33, January, 1982.

    Google Scholar 

  6. I. E. Sutherland and D. Oestreicher, “How Big Should a Printed Circuit Board Be?,” IEEE Transactions on Computers, vol C-22, no. 5, pp. 537–542, May, 1973.

    Google Scholar 

  7. Seraphim, D.P., “Chip-Module-Package Interfaces,” Proceedings of Electronic Insulation Conference, pp. 90–93, September, 1977.

    Google Scholar 

  8. W. E. Donath, “Placement and Average Interconnection Lengths of Computer Logic,” IEEE Transactions on Circuits and Systems, vol CAS-26, no. 4, pp 272–277, April, 1974.

    Google Scholar 

  9. H. B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison Wesley, 1990.

    Google Scholar 

  10. R. Hannemann, “Physical Technology for VLSI Systems,” Proceedings of the International Conference on Computer Design, pp. 48–53, 1986.

    Google Scholar 

  11. L. L. Moresco, “Electronic System Packaging: The Search for Manufacturing the Optimum in a Sea of Constraints,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 13, pp. 494–508, September, 1990.

    Google Scholar 

  12. D. C. Schmidt, “Circuit Pack Parameter Estimation Using Rent’s Rule,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-1, no. 4, pp. 186–192, October, 1982.

    Google Scholar 

  13. D. P. LaPotin, T. R. Mazzawy, and M. L. White, “Early Package Analysis: Considerations and Case Study,” IEEE Computer, vol. 26, no. 4, pp. 30–39, April, 1993.

    Article  Google Scholar 

  14. B. Freyman and R. Pennisi, “Over Molded Pad Array Carrier Package–OMPAC,” Proceedings of the 41st Electronic Components and Technology Conference, pp. 176–185, 1991.

    Google Scholar 

  15. T. S. Steele, “Terminal and Cooling Requirements for LSI Packages,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 4, pp. 187–191, June, 1981.

    Google Scholar 

  16. P. A. Sandborn, “Technology Application Tradeoff Studies in Multichip Systems,” Proceedings of the 1st International Conference on Multichip Modules, pp. 150–158, 1992.

    Google Scholar 

  17. V. W. Antonetti, S. Oktay, and R. E. Simons, “Heat Transfer in Electronic Packages,” in Microelectronics Packaging Handbook, R. R. Tummala and E. J. Rymaszewski editors, Van Nostrand Reinhold, pp. 167–223, 1989.

    Google Scholar 

  18. D. P. Kennedy, “Heat Conduction in a Homogeneous Solid Cylinder of Isotropic Media,” Journal of Applied Physics, vol. 31, no. 8, pp. 490–497, August, 1960.

    Article  Google Scholar 

  19. M. M. Yovanovich, “Thermal Contact Resistance Course Notes,” Presented at the 1989 International Electronics Packaging Conference (IEPS), September, 1989.

    Google Scholar 

  20. T. Dolbear, “Thermal Management of Multichip Modules,” Elec- tronic Packaging and Production, vol. 32, no. 6, pp. 60–63, June, 1992.

    Google Scholar 

  21. D. Q. Kern and A. D. Kraus, Extended Surface Heat Transfer, McGraw-Hill Book Company, 1972.

    Google Scholar 

  22. R. J. Phillips, “Forced-Convection, Liquid-Cooled, Microchannel Heat Sinks,” Technical Report 787, Lincoln Laboratory, Massachusetts Institute of Technology, January, 1988.

    Google Scholar 

  23. D. B. Tuckerman, “Heat-Transfer Microstructures for Integrated Circuits,” Ph.D. Dissertation, Stanford University, February, 1984.

    Google Scholar 

  24. “The NBS-NACA Tables of the Thermal Properties of Gases, NBS ref. W-4391, S50–35.

    Google Scholar 

  25. A. D. Kraus and A. Bar-Cohen, Thermal Analysis and Control of Electronic Equipment, McGraw-Hill Book Company, 1983.

    Google Scholar 

  26. P.A. Sandborn, K. Drake, and R. Ghosh, “Computer Aided Conceptual Design of Multichip Systems,” Proceedings of the Custom Integrated Circuits Conference, pp. 29.4.1–29. 4. 4, 1993.

    Google Scholar 

  27. P. Penfield and J. Rubinstein, “Signal Delay in RC Tree Networks,” Proceedings of the 18th Design Automation Conference, pp. 613–617, 1981.

    Google Scholar 

  28. A. Wilnai, “Open-Ended RC Line Model Predicts MOSFET IC Response,” Electronic Design News, vol. 16, pp. 53–54, 1971.

    Google Scholar 

  29. K. C. Gupta, R. Garg, and R. Chadha, Computer-Aided Design of Microwave Circuits, Artech House, Inc., 1981.

    Google Scholar 

  30. E. E. Davidson, “The Performance Choice: A Study of Chip and Package Densities,” Proceedings of the 40th Electronic Components and Technology Conference, pp. 147–151, 1990.

    Google Scholar 

  31. G. A. Katopis, “Electrical Interconnection Design for High Performance Machines,” Proceedings of the National Electronic Packaging and Production Conference (NEPCON-West), pp. 169–177, 1990.

    Google Scholar 

  32. D. Balderes and M. White, “Packaging Effects on CPU Performance of Large Commercial Processors,” Proceedings of the 35th Electronic Components Conference, pp. 351–356, 1985.

    Google Scholar 

  33. V. K. Nagesh, D. Miller, and L. Moresco, “A Comparative Study of Interconnect Technologies,” Proceedings of the International Electronics Packaging Symposium (IEPS), pp. 433–443, 1989.

    Google Scholar 

  34. R. Kaw, “Comparison of Chip Crossing Delay in Various Packaging Environments,” Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers, pp. 233–236, 1989.

    Google Scholar 

  35. T. R. Gheewala, “System Level Comparison of High Speed Technologies,” Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers, pp. 245–250, 1984.

    Google Scholar 

  36. ] IEEE Split Rock Workshop, 1985.

    Google Scholar 

  37. R. Hannemann, “Interconnects and Packaging for Highly Integrated Systems,” Presented at SPIE International Conference on Advances in Interconnect and Packaging, 1990.

    Google Scholar 

  38. D. L. Carter and D. F. Guise, “Analysis of Signal Propagation Delays and Chip Level Performance Due to On-Chip Interconnections,” Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers, pp. 218–221, 1983.

    Google Scholar 

  39. R. W. Keyes, “A Figure of Merit for IC Packaging,” IEEE Journal of Solid State Circuits, vol. 13, no. 2, pp. 265–266, February 1978.

    Article  Google Scholar 

  40. ] ITT, Reference Data for Radio Engineers,5th edition, Howard W. Sams and Co., 1968.

    Google Scholar 

  41. G. A. Katopis, “Methodology and Computer Aids for the Noise Tolerance of ECL Logic Gates,” Proceedings of the 12th Asilomar Conference on Circuits, Systems and Computers, pp. 500–505, 1979.

    Google Scholar 

  42. W. R. Blood, MECL System Design Handbook, Motorola Inc., 1988.

    Google Scholar 

  43. I. Catt, “Crosstalk (Noise) in Digital Systems,” IEEE Transactions on Electronic Computers, vol. EC-16, pp. 743–763, 1967.

    Google Scholar 

  44. P. M. Duncan, D. L. Fett, A. H. Mones, and T. R. Poulin, “Noise Characteristics on High Density TAB Configurations,” Proceedings of the National Electronic Packaging and Production Conference (NEPCON-West), pp. 638–649, 1990.

    Google Scholar 

  45. A. J. Rainal, “Computing Inductive Noise of Chip Packages,” ATandT Bell Laboratories Technical Journal, vol. 63, pp. 177–195, 1984.

    Google Scholar 

  46. R. Kaw, R. Liu, K. Lee, and R. Crawford, “Effective Inductance for Switching Noise in Single Chip Packages,” Proceedings of the Tenth Annual International Electronics Packaging Conference, pp. 756–761, 1990.

    Google Scholar 

  47. A. T. Baba, W. D. Carlomagno, D. E. Cummings, and F. Guerrero, “Bonded Interconnect Pin (BIP) Technology, A Bare Chip Connection Process for Multichip Modules,” Proceedings National Electronic Packaging and Production Conference (NEPCON-West), pp. 1167–1177, 1991.

    Google Scholar 

  48. P. Robock, and L. T. Nguyen, “Plastic Packaging,” in Microelectronic Packaging Handbook, R.R. Tummala and E.J. Rymaszewski editors, Van Norstrand Reinhold, pp. 523–672, 1989.

    Google Scholar 

  49. N. G. Koopman, T. C. Reiley, and P. A. Totta, “Chip-to-Package Interconnections,” in Microelectronic Packaging Handbook, R.R. Turnmala and E.J. Rymaszewski editors, Van Norstrand Reinhold, pp. 361–453, 1989.

    Google Scholar 

  50. E. E. Davidson, “Electrical Design of a High Speed Computer Packaging System,” IEEE Transactions of Components, Hybrids, and Manufacturing Technology, vol. CHMT-6, pp. 272–282, 1983.

    Google Scholar 

  51. G. A. Katopis, “Delta-I Noise Specification for a High-Performance Computing Machine,” Proceedings of the IEEE, vol. 73, pp. 1405–1415, 1985.

    Article  Google Scholar 

  52. P. A. Sandborn, H. Hashemi, and B. Weigler, “Switching Noise in a Medium Film Copper/Polyimide Multichip Module,” Proceedings of the SPIE International Conference on Advances in Interconnection and Packaging, SPIE vol. 1390, pp. 177–186, 1990.

    Google Scholar 

  53. H. Hashemi, P. A. Sandborn, D. Disko, and R. Evans, R., “The Close Attached Capacitor: A Solution to Switching Noise Problems,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology, vol. 15, pp. 1056–1063, December, 1992.

    Google Scholar 

  54. R. Senthinathan, G. Tubbs, and M. Schuelein, “Negative Feedback Influence on Simultaneously Switching CMOS Outputs,” Proceedings of the Custom Integrated Circuits Conference, pp. 5.4.1–5. 4. 5, 1988.

    Google Scholar 

  55. R. F. Pease, B. W. Langley, and O. K. Kwon, “Simultaneous Switching Noise in Multichip Packaging,” SRC Technical Report T89067, Stanford University, pp. 29–38, 1989.

    Google Scholar 

  56. C. M. Val and J. E. Martin, “A New Chip Carrier for High Performance Applications Integrated Decoupling Capacitor Chip Carrier ‘IDCCC’,” Proceedings of the International Electronics Packaging Conference, pp. 143–159, 1988.

    Google Scholar 

  57. H. Hashemi, U. Ghoshal, K. Ziai, and P. A. Sandborn, “Analytical and Simulation Study of Switching Noise in CMOS Circuits,” Proceedings of the International Electronics Packaging Conference, pp. 762–773, 1990.

    Google Scholar 

  58. R. E. Canright, “A Formula to Model Delta-I Noise,” Proceed- ings of the 37th Electronic Components Conference, pp. 354–361, 1987.

    Google Scholar 

  59. J. C. Laprie and A. Costes, “Dependability: A Unifying Concept for Reliable Computing,” FTCS-12 Digest of Papers, pp. 18–21, 1982.

    Google Scholar 

  60. P. Edmond, A. P. Gupta, D. P. Siewiorek, and A. A. Brennan, “ASSURE: Automated Design for Dependability,” Proceedings of the 27th Design Automation Conference, pp. 555–560, 1990.

    Google Scholar 

  61. D. C. Boose and J. M. Hsiao, “Model for Transient and Permanent Error Detection and Fault-Isolation Coverage,” IBM Journal of Research and Development, vol. 26, no. 1, pp. 67–77, January, 1982.

    Article  Google Scholar 

  62. U.S. Department of Defense, Rome Air Development Center, “Reliability Prediction of Electronic Equipment, MIL-HDBK-217F,” March, 1991.

    Google Scholar 

  63. R. J. Allen and W. J. Roesch, “Reliability Prediction: The Applicability of High Temperature Testing,” Solid State Technology, vol. 33, pp. 103–108, September, 1990.

    Google Scholar 

  64. P. A. Tobias and D. C. Trinidade, Applied Reliability, Van Nostrand Reinhold Company, 1986.

    Google Scholar 

  65. M. Pecht, M. Dasgupta, D. Barker, and C. Leonard, “A Reliability Physics Approach to Failure Prediction Modeling,” Quality and Reliability Engineering International, vol. 6, no. 4, pp. 267–273, September-October, 1990.

    Google Scholar 

  66. B. T. Murphy, “Cost-Size Optima in Monolithic Integrated Circuits,” Proceedings of the IEEE, vol. 52, pp 1537–1545, December, 1964.

    Google Scholar 

  67. R. B. Seeds, “Yield, Economic, and Logistic Models for Complex Digitial Arrays,” Proceedings of the IEEE International Convention Record, Part 6, pp. 60–61, 1967.

    Google Scholar 

  68. T. W. Williams and N. C. Brown, “Defect Level as a Function of Fault Coverage,” IEEE Transactions on Computers, vol. C-30, no. 12, pp. 987–988, December, 1981.

    Google Scholar 

  69. V. D. Agrawal, S. C. Seth, and P. Agrawal, “Fault Coverage Requirement in Production Testing of LSI Circuits,” IEEE Journal of Solid State Circuits, vol. SC-17, pp. 57–61, February, 1982.

    Google Scholar 

  70. G. Messner, “Price/Density Tradeoffs of Multichip Modules,” Proceedings of the International Symposium on Hybrid Microelectronics (ISHM), pp. 28–36, 1988.

    Google Scholar 

  71. J. W. Balde, “Crisis in Technology: The Questionable U.S. Ability to Manufacture Thin Film Multichip Modules,” Proceedings of the IEEE, vol. 80, no. 12, pp. 1995–2002, December, 1992.

    Article  Google Scholar 

  72. C. Lassen, “Integrating Multi-Chip Modules into Electronic Equipment: The Technical and Commercial Trade-Offs,” Proceedings of the Tenth Annual International Electronics Packaging Conference, pp. 3–15, 1990.

    Google Scholar 

  73. D. G. Kelemen, “Cost Considerations in High-Density Packaging,” Proceedings of the Ninth Annual International Electronics Packaging Conference, pp. 1216–1222, 1989.

    Google Scholar 

  74. L. H. Ng, “MCM Package Selection: Cost Issues,” in Multichip Module Technologies and Alternatives–The Basics, D. A. Doane and P. Franzon editors, Van Nostrand Reinhold, pp. 133–164, 1993.

    Google Scholar 

  75. G. R. Weihe, “High Density Multichip Solutions,” Proceedings of the National Electronic Packaging and Production Conference (NEPCON-West), pp. 1121–1129, 1991.

    Google Scholar 

  76. M. Abadir, A. Parikh, L. Bal, P. Sandborn, and C. Murphy, “High Level Test Economics Advisor (Hi-TEA),” Proceedings of the International Workshop on the Economics of Design, Test, and Manufacturing, 1993.

    Google Scholar 

  77. J. K. Hagge and R. J. Wagner, “High-Yield Assembly of Multichip Modules Through Known-Good IC’s and Effective Test Strategies,” Proceedings of the IEEE, vol. 80, no. 12, pp. 1965–1994, December, 1992.

    Article  Google Scholar 

  78. P. A. Sandborn and H. Hashemi, “A Design Advisor and Model Building Tool for the Analysis of Switching Noise is Multichip Modules,” Proceedings of the International Symposium on Microelectronics (ISHM), pp. 652–657, 1990.

    Google Scholar 

  79. G. Choksi, B. K. Bhattacharyya, S. Stys, and B. Natarajan, “Computer Aided Electrical Modeling of VLSI Packages,” Proceedings of the 40th Electronic Components and Technology Conference, pp. 169–172, 1990.

    Google Scholar 

  80. S. A. Elkind, Lamda; A MIL-217D System Failure Rate Analysis Program User’s Manual, ECE Department, Carnegie Mellon University, 1983.

    Google Scholar 

  81. A. M. Johnson Jr. and M. Malek, “Survey of Software Tools for Evaluating Reliability, Availability, and Serviceability,” ACM Computing Surveys, pp. 227–269, 1988.

    Google Scholar 

  82. A. A. Brennan, “Automatic Synthesis for Reliability,” Research Report No. CMUCAD-88–3, Carnegie Mellon University, January, 1988.

    Google Scholar 

  83. Computer Aided Design of IC, Hybrid, and MCM Packages - CADMP,“ CALCE Electronic Packaging Research Center, University of Maryland, 1992.

    Google Scholar 

  84. K. Srihari and C. R. Emerson, “Knowledge Based Manufacturing Problem Diagnosis in PCB Assembly,” Proceedings of the Twelfth Annual International Electronics Packaging Conference, pp. 245–257, 1992.

    Google Scholar 

  85. D. L. Hilbert, “The Integrated Product Engineering Expert System (IPEX) A Design/Producibility Advisor,” Proceedings of the National Electronic Packaging and Production Conference (NEPCON-West), pp. 157–163, 1992.

    Google Scholar 

  86. Y. Ogawa, T. Itoh, Y. Miki, T. Ishii, Y. Sato, and R. Toyoshima, “Timing-and Constraint-Oriented Placement for Interconnected LSIs in Mainframe Design,” Proceedings of the 28th Design Automation Conference, pp. 253–258, 1991.

    Google Scholar 

  87. M. D. Osterman and M. Pecht, “Placement for Reliability and Routability of Convectively Cooled PWB’s,” IEEE Transactions on Computer-Aided Design, vol. 9, pp. 734–744, 1990.

    Article  Google Scholar 

  88. W. W.-M. Dai, “Performance Driven Layout of Thin Film Multichip Modules,” Proceedings of the SRC Topical Research Conference on Packaging Design, Analysis, and Simulation, pp. 35–37, 1991.

    Google Scholar 

  89. H. B. Bakoglu and J. D. Meindl, “A System Level Circuit Model for Multi-and Single-Chip CPU’s,” Proceedings of the IEEE International Solid State Circuits Conference, pp. 308–309, 1987.

    Google Scholar 

  90. H. B. Bakoglu, “Circuit and System Performance Limits on ULSI: Interconnections and Packaging,” Ph.D. Dissertation, Stanford University, 1987.

    Google Scholar 

  91. W. E. Pence, “Electrical, Thermal, and Architecture Aspects of VLSI Packaging and Interconnects for High-Speed Digital Computers,” Ph.D. Dissertation, Cornell University, 1989.

    Google Scholar 

  92. J. P. Krusius, “System Interconnection of High Density Multi-Chip Modules,” Proceedings of the SPIE Vol. 1390 International Conference on Advances in Interconnects and Packaging, SPIE vol. 1390, pp. 261–270, 1990.

    Google Scholar 

  93. W. P. Birmingham, “Automated Knowledge Acquisition for a Hierarchical Synthesis System”, Ph.D. Dissertation, Carnegie Mellon University, 1988. (also published as CMU Research Report No. CMUCAD-88–25).

    Google Scholar 

  94. W. P. Birmingham, A. P. Gupta, and D. P. Siewiorek, “The MI-CON System for Computer Design,” Proceedings of the 26th Design Automation Conference, pp 135–140, 1989.

    Google Scholar 

  95. W. P. Birmingham, A. P. Gupta, and D. P. Siewiorek, Automating the Design of Computer Systems - The MICON Project, Jones and Bartlett Publishers, Boston, MA., 1992

    MATH  Google Scholar 

  96. T. Sone, K. Kaizu, and M. Hirai, “A Knowledge Base Construction for Technology Planning of Electronic Equipments,” Proceedings of the National Convention of the Institute of Electronics, Information and Communications Engineers (Japan), vol. 6, p. 107, Spring 1989.

    Google Scholar 

  97. P. A. Sandborn, “A Software Tool for Technology Tradeoff Evaluation in Multichip Packaging,” Proceedings of the Eleventh International Electronics Manufacturing Technology Symposium (IEMT), pp. 337–341, 1991.

    Google Scholar 

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  1. Microelectronics and Computer Technology Corporation (MCC), USA

    Peter A. Sandborn & Hector Moreno

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Sandborn, P.A., Moreno, H. (1994). Tradeoff Analysis. In: Conceptual Design of Multichip Modules and Systems. The Springer International Series in Engineering and Computer Science, vol 250. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-4841-3_3

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