Abstract
Consider the processor sharing node (PSN) of Figure 3.1 which is, for our purposes, a switch output port as well. A PSN consists of a bank of synchronized, discrete-time FIFO queues sharing an output link with a service capacity of one cell per unit time (c cells/s). Let N be the number of FIFO queues that have bandwidth guarantees, e.g., FIFO queues handling CBR or VBR traffic.
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Kesidis, G. (1996). Bandwidth Scheduling for a Single Node. In: ATM Network Performance. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-4568-9_3
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DOI: https://doi.org/10.1007/978-1-4757-4568-9_3
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