Abstract
Motivated by the commercial success of the wireline communication products, mixed-signal designers are being pushed to integrate A/D and D/A interfaces featuring 12- to 16-bit effective resolution for signal bandwidths well in excess of 1MHz [1]. These specifications must be achieved in a low-voltage scenario, making use of poor performance (and often badly characterized) devices, which decreases the “analog speed” of deep-submicron CMOS processes.
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Medeiro, F., del Río, R., de la Rosa, J.M., Pérez-Verdú, B., Rodríguez-Vázquez, A. (2003). High-order Cascade Multi-bit ΣΔ Modulators. In: Rodríguez-Vázquez, A., Medeiro, F., Janssens, E. (eds) CMOS Telecom Data Converters. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-3724-0_9
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