Non-Hanan Optimization for Global VLSI Interconnect

Abstract

Under current Very Large Scale Integration (VLSI) technology, tens of millions of transistors can be integrated on a single chip, and future trends show that circuit sizes will continue to increase exponentially. Under this scenario, the performance bottleneck will shift to the delays associated with the metal wires, or interconnect, used to join these transistors. In the future, as transistor feature sizes become progressively smaller, the switching speed of a transistor driving a minimum load will become faster. On the other hand, as interconnect wires become thinner and longer, the interconnect delay for global wires is projected to increase, relative to the gate delay, due to the increased wire resistance. Both trends lead interconnect delay to dominate logic delay and become a significant bottleneck in VLSI system performance [1]. As a result, many efforts have been carried out in recent years to improve the interconnect performance, and a good overview of these works is provided in [2–4].