Skip to main content
SpringerLink
Log in

Device Physics and Electrical Performance of Bulk Silicon Mosfets

  • Chapter
Device and Circuit Cryogenic Operation for Low Temperature Electronics

Abstract

Low temperature operation of Silicon CMOS transistors may be considered as a promising way to improve the device and circuit performances. The temperature reduction allows a substantial increase of the carrier mobility and saturation velocity, better turn-on capabilities, latch-up immunity, reduction in activated degradation processes, lower power consumption, decrease of leakage current, reduced thermal noise, increased thermal conductivity, etc [1–12]. Nevertheless, the low temperature operation leads to some problems and difficulties related to specific cryogenic conditions. For instance, the impurity freeze-out, kink phenomenon, series resistance effects, transient behavior, changes in mobility laws make it difficult the physical understanding and modeling of MOS devices operated at low temperature (4.2–300K).

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. F. Fang, A. B. Fowler, “Hot electron effect and saturation velocity in silicon inversion layers”, J. Appl. Phys., 41, 1825 (1970).

    Article  Google Scholar 

  2. see special issue of IEEE Trans Electron Dev., 36 (1986).

    Google Scholar 

  3. R. K. Kirschman, “Cold electronics: an overview”, Cryogenics, 25, 115 (1985).

    Article  Google Scholar 

  4. N. S. Saks, A. Nordbryn, “Time dependence of depletion region formation in phosphorus doped silicon MOS devices at cryogenic temperatures”, J. Appl. Phys., 50, 6962 (1979).

    Article  Google Scholar 

  5. S. Tewksbury, “Transient response of n-channel metal-oxide-semiconductor field effect transistors during turn-on at 10–25K”, J. Appl. Phys., 53, 3865 (1982).

    Article  Google Scholar 

  6. J. C. Woo, J. D. Plummer, “Short channel effect in MOSFETs at liquid nitrogen temperature”, IEEE Trans Electron Dev., ED-33, 1012 (1986).

    Article  Google Scholar 

  7. C. Huang, S. Gildenblat, “Measurements and modelling of the n-channel MOSFET inversion layer mobility and device characteristics in the temperature range 60–300K”, IEEE Trans Electron Dev., ED-37, 1289 (1990).

    Article  Google Scholar 

  8. F. Balestra, L. Audaire, C. Lucas, “Influence of substrate freeze-out on the characteristics of MOS transistors at very low temperature”, Solid State Electron, 30, 321 (1987).

    Article  Google Scholar 

  9. E. Simoen, B. Dierickx, L. Warmerdam, J. Vermeiren, C. Claeys, “Freeze-out effects on NMOS transistor characteristics at 4.2K”, IEEE Trans Electron Dev., ED-36, 1155 (1989).

    Article  Google Scholar 

  10. I. M. Hafez, G. Ghibaudo, F. Balestra, “Reduction of kink effect in short channel MOS transistors”, IEEE Electron Device Lett., EDL-11, 120 (1990).

    Article  Google Scholar 

  11. F. Balestra, G. Ghibaudo, “Brief review of the MOS device physics for low temperature electronics”, Solid State Electron, 37, 1967 (1994).

    Article  Google Scholar 

  12. W. F. Clark, B. El-Kareh, R. Pires, S. L. Titcomb, R. L. Anderson, “Low temperature CMOS: A brief review”, IEEE Trans Components Hybrids and Manufacturing Technology, CHMT-15, 397 (1992).

    Article  Google Scholar 

  13. T. Ando, A. Fowler and F. Stern, “Electronic properties of two-dimensional systems”, Rev. Mod. Phys., 54, 437 (1982).

    Article  Google Scholar 

  14. F. Stern, “Quantum properties of surface space-charge layers”, CRC Critical Rev. Solid-St. Sci., 5, 499 (1974).

    Google Scholar 

  15. C. Moglestue, “Self-consistent calculation of electron and hole inversion charges at silicon-silicon dioxide interfaces”, J. Appl. Phys., 59, 3175 (1986).

    Article  Google Scholar 

  16. G. Ghibaudo, “Transport in the inversion layer of a MOS transistor: use of Kubo-Greenwood formalism”, J. Phys., C 19, 767 (1985).

    Google Scholar 

  17. J. Pals, “Measurements of the surface quantization in silicon n-and p-type inversion layers at temperatures above 25 K”, Phys. Rev., B7, 754 (1973).

    Google Scholar 

  18. K. Von Klitzing, G. Dorda and M. Pepper, “New method for high-accuracy determination of the fine-structure constant based on quantized Hall resistance”, Phys. Rev. Lett., 45, 494 (1980).

    Article  Google Scholar 

  19. M. J. Van Dort, P. H. Woerlee A. J. Walker, C. A. H. Juffermans and H. Lifka, “Effects of high normal electric fields in deep submicron MOSFET’s”, Microelectron. Eng., 15, 551 (1991).

    Article  Google Scholar 

  20. C. T. Sah, T. Ning and L. Tschopp, “The scattering of electrons by surface oxide charges and by lattice vibrations at the silicon-silicon dioxide interface”, Surf. Sciences, 32, 561 (1972).

    Article  Google Scholar 

  21. S. Kawaji, “The two-dimensional lattice scattering mobility in a semiconductor inversion layer”, J. Phys. Soc. Japan, 27, 906 (1969).

    Article  Google Scholar 

  22. F. Stern, “Calculated temperature dependence of mobility in silicon inversion layers”, Phys. Rev. Lett., 44, 1469 (1980).

    Article  Google Scholar 

  23. G. Ghibaudo and F. Balestra, “Modelling of ohmic MOSFET operation at very low temperature”, Solid St. Electron., 31, 105 (1988).

    Article  Google Scholar 

  24. F. Fang and A. Fowler, “Transport properties of electrons in inverted silicon surfaces”, Phys. Rev. B3, 619 (1968).

    Article  Google Scholar 

  25. T. Sato, Y. Takeishi and H. Hara, “Mobility anisotropy of electrons in inversion layers on oxidized silicon surfaces”, Phys. Rev., B4, 1950 (1971).

    Google Scholar 

  26. A. Emrani, Ph. D. Thesis dissertation, INP Grenoble (1992).

    Google Scholar 

  27. S. C. Sun, J. D. Plummer, “Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces”, IEEE Trans Electron Dev., ED-27, 1497 (1980).

    Article  Google Scholar 

  28. A. Hairapetian, D. Gitlin, C. R. Viswanathan, “Low temperature mobility measurements in CMOS devices. ”, IEEE Trans Electron Dev., ED-36, 1448 (1989).

    Article  Google Scholar 

  29. A. Emrani, F. Balestra, G. Ghibaudo, “Generalized mobility law for drain current modeling in Si MOS transistors from liquid helium to room temperature”, IEEE Trans Electron Dev., ED-40, 564 (1993).

    Article  Google Scholar 

  30. A. Emrani, F. Balestra, G. Ghibaudo, “On the understanding of electron and hole mobilitiy models from room to liquid helium temperatures”, Solid State Electron, 37, 1723 (1994).

    Article  Google Scholar 

  31. K. Rais, F. Balestra, G. Ghibaudo, “On the high electric field mobility behavior in Si MOSFETs from room to liquid helium temperature”, Phys. Status Solidi (a), 145, 217 (1994).

    Article  Google Scholar 

  32. K. Rais, F. Balestra, G. Ghibaudo, “Surface roughness mobility model for silicon MOS transistor”, Phys. Status Solidi (a), 146, 853 (1994).

    Article  Google Scholar 

  33. A. Emrani, G. Ghibaudo, F. Balestra, “On the universal electric field dependence of the electron and hole effective mobility in MOS inversion layers”, Solid State Electron, 37, 111 (1994).

    Article  Google Scholar 

  34. A. Modelli, S. Manzini, “High drift velocity of electrons in silicon inversion layers”, Solid State Electron, 31, 99 (1988).

    Article  Google Scholar 

  35. K. Rais, G. Ghibaudo, F. Balestra, M. Dutoit, “Study of saturation velocity overshoot in deep submicron silicon MOSFETs from liquid helium up to room temperature”, J. Phys. IV, C6, p. 19 (1994).

    Google Scholar 

  36. G. Shahidi, D. Antoniadis, H. Smith, “Electron velocity overshoot at room and liquid nitrogen temperatures in silicon inversion layers”, IEEE Electron Device Lett., EDL-9, 94 (1988).

    Article  Google Scholar 

  37. S. Laux, M. Fischietti, “Monte Carlo simulation of submicrometer Si-n MOSFETs at 77 and 300K”, IEEE Electron device Lett., EDL-9, 467 (1988).

    Article  Google Scholar 

  38. J. B. Roldan, F. Gamiz, J. A. Lopez-Villanueva, J. E. Carceller, « Modeling effects of electron-velocity overshoot in a MOSFET », IEEE Trans Electron Devices., ED-44, 841 (1997).

    Article  Google Scholar 

  39. J. B. Roldan, F. Gamiz, J. A. Lopez-Villanueva, P. Cartujo, J. E. Carceller, « A model for the drain current of deep submicrometer MOSFETs including electron-velocity overshoot », IEEE Trans Electron Devices., ED-45, 2249 (1998).

    Article  Google Scholar 

  40. I. M. Hafez, G. Ghibaudo, F. Balestra, M. Haond, “Impact of LDD structures on the operation of silicon MOSFETs at low temperature”, Solid State Electron, 38, 419 (1995).

    Article  Google Scholar 

  41. I. M. Hafez, G. Ghibaudo, F. Balestra, “Analysis of the kink effect in MOS transistors”, IEEE Trans Electron Dev., ED-37, 818 (1990).

    Article  Google Scholar 

  42. D. Foty, “Impurity ionization in MOSFETs at very low temperature”, Cryogenics, 30, 1056 (1990).

    Article  Google Scholar 

  43. E. Simoen, B. Dierickx, L. Deferm, C. Claeys, G. Declerck, “The charge transport in a silicon resistor at liquid helium temperature”, J. Appl. Phys., 68, 4091 (1990).

    Article  Google Scholar 

  44. S. M. Sze, Physics of Semiconductor Devices (New York: Wiley, 1981).

    Google Scholar 

  45. N. Arora and M. S. Sharma, “Modeling the anomalous threshold voltage behavior of submicrometer MOSFET’s”, IEEE Electron Device Letters, EDL-13, 92 (1992).

    Article  Google Scholar 

  46. C. S. Rafferty, H. H. Vuong, S. A. Eshraghi, M. D. Giles, M. R. Pinto, S. J. Hillenius, “Explanation of reverse short channel effect by defect gradients”, IEDM Technical Digest, p. 311 (1993).

    Google Scholar 

  47. H. Jacobs, A. V. Schwerin, D. Scharfetter, F. Lau, “MOSFET reverse short channel effect due to silicon interstitial capture in gate oxide”, IEDM Technical Digest, p. 307 (1993).

    Google Scholar 

  48. A. Kalnitsky, R. Frijns, C. Mallardeau, E. Daemen, M. Bonis, M. Varrot, M. T. Basso, R. Penning de Vries, “Suppression of the Vt roll-up effect in sub-micron NMOST”, Proc. ESSDERC 94, p. 377.

    Google Scholar 

  49. M. Nishida and H. Onodera, “An anomalous increase of threshold voltages with shortening the channel lengths for deeply boron-implanted n-channel MOSFETs”, IEEE Trans Electron Devices, ED-28, 1101 (1981).

    Article  Google Scholar 

  50. M. Orlowski, C. Mazure and F. Lau, “Submicron short channel effects due to gate reoxidation induced lateral interstitial diffusion”, IEDM Technical Digest, p. 632 (1987).

    Google Scholar 

  51. C. Y. Lu and J. M. Sung, “Reverse short-channel effects on threshold voltage in submicrometer salicide devices”, IEEE Electron Device Lett., EDL-10, 446 (1989).

    Article  Google Scholar 

  52. H. Hanafi, W. P. Noble, R. S. Bass, K. Varahramyan, Y. Lii, A. J. Dally, “A model for short channel behavior in submicron MOSFETs”, IEEE Electron Device Lett., EDL-14, 575 (1993).

    Article  Google Scholar 

  53. M. J. Van Dort, H. Lifka, P. C. Zalm, R. C. M. De Kruif, W. B. De Boer, P. H. Woerlee, C. A. H. Juffermans, A. J. Walker, J. W. Slotboom and N. E. B. Cowern, “A high-resolution study of two-dimensional oxidation-enhanced diffusion in silicon”, IEDM Technical Digest, p. 299 (1993).

    Google Scholar 

  54. B. Yu, C. Wann, E. Nowak, K. Noda, C. Hu, “Short-channel effect improved by lateral channel-engineering in deep-submicronmeter MOSFET’s”, IEEE Trans Electron Devices, ED-44, 627 (1997).

    Google Scholar 

  55. H. Brut, A. Juge and G. Ghibaudo, “Physical model of threshold voltage in silicon MOS transistors including reverse short channel effect”, Electronics Letters, 31, 411 (1995).

    Article  Google Scholar 

  56. B. Szelag, F. Balestra and G. Ghibaudo, “Comprehensive analysis of reverse short-channel effect in silicon MOSFETs from low-temperature operation”, Electron Device letters, EDL-19, 511 (1998).

    Article  Google Scholar 

  57. T. Grotjohn, B. Hoefflinger, “A parametric short channel MOS transistor model for subthreshold and strong inversion current”, IEEE Trans Electron Dev., ED-31, 234, 1984.

    Article  Google Scholar 

  58. S. Chamberlain, S. Ramanan, “Drain induced barrier lowering analysis in VLSI MOSFET devices using two dimensional numerical simulations”, IEEE Trans Electron Dev., ED-33, 1745 (1986).

    Article  Google Scholar 

  59. W. Fikry, G. Ghibaudo, M. Dutoit, “Temperature dependence of drain induced barrier lowering in deep submicrometer MOSFETs”, Electron Lett., 30, 911 (1994).

    Article  Google Scholar 

  60. G. Bertrand, S. Deleonibus, D. Souil, C. Caillat, G. Guegan, S. Tedesco, M. Heitzmann, P. Mur, F. Balestra, “Ultimate sub 25 nm gate length NMOSFETs transport at 293K and 77K”, Silicon Nanoelectronics Workshop, Honolulu, USA (June 2000) p. 68.

    Google Scholar 

  61. J. Chen, T. Y. Chan, I. C. Chen, P. K. Ko, C. Hu, “Sub breakdown drain leakage current in MOSFET”, IEEE Electron Device Lett., EDL-8, 515 (1987).

    Article  Google Scholar 

  62. K. Kurimoto, Y. Odake, S. Odanak, “Drain leakage current characteristics due to band to band tunneling in LDD MOS devices”, IEDM Tech Digest, p. 621 (1989).

    Google Scholar 

  63. K. Rais, F. Balestra, G. Ghibaudo, “Temperature dependence of gate induced drain leakage in silicon MOS devices”, Electron Lett., 30, 32 (1994).

    Article  Google Scholar 

  64. K. Rais, G. Ghibaudo, F. Balestra, “Temperature dependence of substrate currrent in silicon CMOS devices”, Electron Lett., 29, 778 (1993).

    Article  Google Scholar 

  65. N. D. Arora, M. S. Sharma, “MOSFET substrate current model for circuit simulation”, IEEE Trans Electron Dev., ED-38, 1392 (1991).

    Article  Google Scholar 

  66. A. K. Henning, N. N. Chan, J. T. Watt, J. D. Plummer, “Substrate current at cryogenic temperatures: measurements and two-dimensional model for CMOS technology”, IEEE Trans Electron Dev., ED-34, 64 (1987).

    Article  Google Scholar 

  67. T. Y. Chan, P. K. Ko, C. Hu, “A simple method to characterize the substrate current in MOSFETs”, IEEE Electron device Lett., EDL-5, 505 (1984).

    Article  Google Scholar 

  68. B. Szelag, M. Dutoit, F. Balestra, “Hot carrier effects in deep submicron bulk silicon MOSFETs”, Solid State Electronics, 42, 42 (1997).

    Google Scholar 

  69. F. Balestra, Matsumoto T., Tsuno M., Koyanagi M., “New experimental findings on hot carrier effects in sub−0.1 mu m MOSFETs”, IEEE Electron Device Lett., EDL-16, 433 (1995).

    Article  Google Scholar 

  70. S. I. Takagi and Toriumi A., “New experimental findings on hot carrier transport under velocity saturation regime in Si MOSFETs”, Proc. IEEE/IEDM, p. 711, (1992).

    Google Scholar 

  71. C. Hu, S. Tarn, F-C. Hsu, P. K. Ko, T. Y. Chan, K. W. Terrill, K. Terrill “Hot-Electron Induced MOSFET Degradation-Model, Monitor, Improvement,” IEEE Trans. Electron Devices, ED-32, 375 (1985).

    Google Scholar 

  72. J. D. Bude and M. Matrapasqua, “Impact ionization and distribution functions in sub-micron nMOSFET technologies”, IEEE Elec. Dev. Lett., EDL-16, 439 (1995).

    Article  Google Scholar 

  73. J. Masunaga, Kohyama S., Konaka M., Iizuka H., “Design limitations due to substrate currents and secondary impact ionization electrons in NMOS”, Jap. J. Appl. Phys., 19, Suppl. 19-1, 93 (1979).

    Google Scholar 

  74. B. Marchand, B. Cretu, G. Ghibaudo, F. Balestra, D. Blachier, C. Leroux, S. Deleonibus, G. Guégan, G. Reimbold, S. Kubicek, K. DeMeyer, “Secondary impact ionization and device aging in deep submicron MOS devices with various transistor architectures”, Proc. ULIS’2000, Grenoble, p. 9 (Jan. 2000).

    Google Scholar 

  75. B. Marchand, D. Blachier, G. Ghibaudo, C. Leroux, F. Balestra and G. Reimbold, “Generation of hot carriers by secondary impact ionization in deep submicron devices: model and light emission characterization”, IEEE Int Reliability Physics Symposium, IRPS 2000, San Jose, CA, USA (April 2000) p. 93

    Google Scholar 

  76. A. Raychaudhuri, Deen J., Kwan W. S., King M., “Features and mechanisms of the saturating hot-carrier degradation in LDD NMOSFETs”, IEEE Trans. Electron Dev., ED-43, 1114 (1996).

    Article  Google Scholar 

  77. J. Bude, Iizuka T., Kamakura Y., “Determination of threshold energy for hot electron interface state generation”, IEDM Tech Dig., p. 865 (1996).

    Google Scholar 

  78. Takeda et al., Hot carrier effects in MOS devices, Academic Press, p. 123, 1995.

    Google Scholar 

  79. J. Wang-Ratkovic, R. Lacoe, K. MacWilliams, M. Song, S. Brown, G. Yabiku, “New understanding of LDD NMOS hot carrier degradation and device lifetime at cryogenic temperatures”, Microelectron. Reliab., 37, 1747 (1997).

    Article  Google Scholar 

  80. B. Cretu, F. Balestra and G. Ghibaudo, “A comparative study of hot carrier degradation in deep submicron MOSFETs at room and liquid nitrogen temperatures”, Proc. of Workshop on low temperature electronics, WOLTE 4, June 2000, ESA Editions, p. 35.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Laboratoire de Physique des Composants à Semiconducteurs, UMR CNRS, ENSERG/INPG, 23 rue des Martyrs, BP 257, 38016, Grenoble, France

    Gérard Ghibaudo & Francis Balestra

Authors
  1. Gérard Ghibaudo
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Francis Balestra
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. UMR CNRS/INPG, Grenoble, France

    Francis Balestra  & Gérard Ghibaudo  & 

Rights and permissions

Reprints and permissions

Copyright information

© 2001 Springer Science+Business Media Dordrecht

About this chapter

Cite this chapter

Ghibaudo, G., Balestra, F. (2001). Device Physics and Electrical Performance of Bulk Silicon Mosfets. In: Balestra, F., Ghibaudo, G. (eds) Device and Circuit Cryogenic Operation for Low Temperature Electronics. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-3318-1_2

Download citation

  • DOI: https://doi.org/10.1007/978-1-4757-3318-1_2

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4419-4898-4

  • Online ISBN: 978-1-4757-3318-1

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation