Abstract
This work presents a design strategy for fully integrated CMOS frequency synthesizers, using the DCS-1800 class I/II standard as driving application. The design of the loop filter is emphasized. The goal is to minimize the integrated capacitance while maintaining the required phase noise and dynamic performance by proper filter topology selection and optimization of the loop parameters. Based on these results, a type-II, fourth-order PLL frequency synthesizer is implemented in a standard 0.25μm CMOS technology, including a monolithic voltage controlled oscillator and a fully integrated loop filter. The measurements show full compliance with the DCS-1800 class I/II specifications, while the occupied area is only 2 × 2 mm2. To conclude, the influence of ∆∑ fractional-N division control on the performance of the PLL frequency synthesizer is discussed.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
W.F. Egan, “Frequency synthesis by Phase Lock”, J. Wiley and Sons, New York, USA, 1981
A.A. Abidi, “Radio-frequency integrated circuits for portable communications”, Proc. Of the IEEE Custom Integrated Circuits Conference (CICC 94), pp. 151–158, 1994.
B. Razavi, “Challenges in the design of frequency synthesizers for wireless applications”, Proc. Of the IEEE Custom Integrated Circuits Conference (CICC 97), pp. 151–158, 1997.
J. Craninckx, “Low-phase-noise fully integrated CMOS frequency synthesizers”, Ph.D. Dissertation, Katholieke Universiteit Leuven, 1997.
P. Kinget, “Integrated GHz Voltage Controlled Oscillators”, Analog Circuit Design, (W.Sansen, J.H.Huijsing and R.J. van de Plassche, eds), pp.353–381, New York: Kluwer Academic Publishers, 1999.
B. Razavi, “A study of phase noise in CMOS oscillators”, IEEE Journal of Solid-State Circuits, vol. 31, no. 3, pp. 331–343, March 1996.
B. De Muer, M. Steyaert, “A single-ended 1.5GHz 8/9 dual-modulus prescaler in 0.7m CMOS with low phase noise and high input sensitivity”, Proc. of the European Solid-State Circuits Conference (ESSCIRC 98), pp. 256–259, The Hague, September 1998.
F.M. Gardner, “Phaselock Techniques”, J. Wiley and Sons, New York, USA, 1979
R.E. Best, “Phase-Locked Loops: design, simulation andapplication”, Third Edition, McGraw-Hill, 1997.
European Digital Cellular Telecommunications System (Phase 2+): Radio transmission and reception“, ETS(I) 300 910 (GSM 05.05 version 5. 4. 1 ).
B. Miller and R.J. Conley,“A multiple modulator fractional divider”, IEEE Trans. On Instrumentation and Measurement, vol. 40, no. 3, pp. 578–583, June 1991.
T.A.D. Riley, M.A. Copeland and T.A. Kwasniewski, “Delta-sigma modulation in fractional-N frequency synthesis”, IEEE Journal of Solid-State Circuits, vol. 28, no. 5, pp. 553–559, May 1993.
D. Mijuskovic, M.J. Bayer, et.al, “Cell based fully integrated CMOS frequency synthesizers”, IEEE Journal of Solid-State Circuits, vol. 29, no. 3, pp. 271–279, March 1994.
B. De Muer, N. Itoh, M. Borremans and M. Steyaert “A 1.8 GHz highly-tunable low-phase-noise CMOS VCO”, Proc. Of the IEEE Custom Integrated Circuits Conference (CICC 00), to be published, 2000.
The Mathworks Inc., “Matlab user’s guide, version 5”, 1997.
Saber User Mnaual“, Analogy, 1996.
B. De Muer, C. De Ranter and M. Steyaert, “A fully integrated 2GHz LC-VCO with phase noise of -125dBc/Hz at 600kHzM, Proc. of the 1999 European Solid- State Circuits Conference (ESSCIRC y 99), pp. 206–209, 1999.
M. Steyaert, J. Janssens, B. De Muer, M. Borremans, N. Itoh, MA 2V CMOS cellular transceiver front-end“, ISSCC Digest of technical papers, pp. 142–143, Feb. 2000
S.R. Norsworthy, R. Schreier, G.C. Temes, “Delta-sigma data converters: theory, design and simulation”, IEEE Press, 1996.
Bar-Giora Goldberg, “Digital techniques in frequency synthesis”, McGraw-Hill, 1995.
A.I. Yasuyki, K. Uchimura, A. Iwata, et al., “A 16-bit oversampling A-to-D conversion technology using triple-integration noise shaping”, IEEE Journal of Solid-State Circuits, vol. 22, no. 6, pp. 921–928, December 1987.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2000 Springer Science+Business Media New York
About this chapter
Cite this chapter
De Muer, B., Steyaert, M. (2000). Fully Integrated CMOS Frequency Synthesizers for Wireless Communications. In: van de Plassche, R.J., Huijsing, J.H., Sansen, W. (eds) Analog Circuit Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-3198-9_14
Download citation
DOI: https://doi.org/10.1007/978-1-4757-3198-9_14
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-5002-4
Online ISBN: 978-1-4757-3198-9
eBook Packages: Springer Book Archive