Speed-Power-Accuracy Trade-off In high-speed Analog-to-digital converters: Now and in the future...

Abstract

High-speed analog-to-digital converters (ADC’ s) are an essential part in a signal processing system. Radar applications and hard disk drive read channels require very high conversion speeds and relatively low resolutions (6–8 bits) [1][4]. Since several ADC’s may be needed in a “system-on-chip”, the ADC should only consume a small fraction of the total power budget [15]. In this article, a fundamental trade-off between speed, power and accuracy for high-speed converters is shown. This trade-off only depends on the matching data of the used process. Technology-scaling issues influencing this trade-off will be discussed. An important factor is the supply voltage; the never-ending story of technology trends towards smaller transistor dimensions has resulted to date in deep sub-micron transistors. The consequence is the downscaling of the power supply voltages, to date even lower than 2V, with almost the same threshold voltages of the CMOS transistors (in order to keep the leakage current in digital circuits small enough). This voltage scaling will have an impact on the previous mentioned trade-off between speed, power and accuracy. In the first section, high-speed ADC’s architectures are presented.

In the second section the impact of mismatch or accuracy in analog circuits (especially in high-speed ADC’s) and the impact on power drain is discussed. Secondly in section three some fundamental limitations of analog integrated circuit design in the trade-off between speed, accuracy and power drain are analysed. In the following section the impact of the supply-voltage scaling on this trade-off is studied. After this, some modifications are presented to circumvent this tradeoff, and the article is ended with a conclusion.