Abstract
Sum-of-products computations are widely used in multimedia and communications systems. Techniques for the power efficient data path synthesis of sum-of-products computations are presented in this chapter. Simple and efficient heuristics for the instruction-level scheduling and assignment steps are described. These steps are crucial sub-steps of the custom processor synthesis stage of the system level design meta-flow proposed in chapter 2. The proposed heuristics exploit the inherent independence of the sum-of-products computations to formulate the synthesis tasks using the concept of the Traveling Salesman’s Problem. In this way the synthesis tasks can be solved very efficiently. Different partly static cost functions are proposed to drive the synthesis tasks. The proposed cost functions target the power consumption either in the buses connecting the functional units with the storage elements or in the functional units. The partly static nature of the proposed cost functions reduces the time of the synthesis procedure. Experimental results from different relevant digital signal processing algorithmic kernels prove that the proposed synthesis techniques lead to significant power savings.
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References
V. Bhaskaran, K. Konstantinides, Image and Video Compression Standards, Kluwer Academic Publishers, 1994.
A. Chatterjee, R. Roy, “Synthesis of low power linear DSP circuits using activity metrics”, International Conference VLSI Design, January 1994, pp. 265–270.
J-M. Chang, M. Pedram, “Module assignment for low power”, ACM/IEEE European Design Automation Conference, September 1996, pp. 376–381.
N. Christofides, “Worst-case analysis of a new heuristic for the travelling salesman problem”, Report 388, Graduate School of Industrial Administration, Carnegie Mellon University, Pittsburgh, PA.
A. Dasgupta, R. Karri, “Simultaneous scheduling and binding for power minimization during microarchitecture synthesis”, ACM/IEEE International Symposium Low Power Design, April 1995, pp. 69–74.
A. G. Dempster and M. D. Mcleod, “Use of minimum adder multiplier blocks in FIR digital filters”, IEEE Transactions on Circuits and Systems II, vol. 42, pp. 569–577, September 1995.
Y. Fang, A. Albicki, “Joint scheduling and allocation for low power”, IEEE International Symposium on Circuits and Systems, May 1996, pp. 556–559.
R. Hartley, “Optimization of CSD multipliers for filter design”, IEEE International Symposium on Circuits and Systems, 1991, pp. IV.1992-IV.1995.
M. Janssen, F. Catthoor, H. De Man, “A specification invariant technique for regularity improvement between flow graph clusters”, European Design Automation Conference, February 1996, pp. 138–143.
H. Kojima, A. Shridhar, “Interlaced accumulation programming for low power DSP”, ACM/IEEE International Symposium Low Power Electronics and Design, August 1996, pp. 213–216.
M. T-C. Lee, V Tiwari, S. Malik, M. Fujita, “Power analysis and minimization techniques for embedded DSP software”, IEEE Transactions Very Large Scale Integration Systems, pp. 123–135, June 1997.
M. Mehendale, S. D. Sherlekar, and G. Venkatesh, “Coefficient optimization for low power realization of FIR filters”, IEEE Workshop VLSI Signal Processing, September 1995, pp. 352–361.
M. Miranda, F. Catthoor, M. Janssen, H. De Man, “High-level address optimisation and synthesis techniques for data transfer intensive applications”, IEEE Transactions Very Large Scale Integration Systems, vol.6, pp. 677 – 686, December 1998.
E. Musoll, J. Cortadella, “High-level synthesis techniques for reducing the activity of functional units”, ACM/IEEE International Symposium Low Power Design, April 1995, pp. 99–104.
H. Nguyen, A. Chatterjee, R. Roy, “Activity measures for fast relative power estimation in numerical transformation for low power DSP synthesis”, Journal of VLSI Signal Processing, Kluwer Academic Publishers, vol. 18, pp. 25–38, January 1998.
C. H. Papadimitriou, K. Steiglitz, Combinatorial Optimisation: Algorithms and Complexity, Prentice-Hall, 1982.
D. Pearson, K. Parhi, “Low power FIR digital filter architecture”, IEEE International Symposium Circuits and Systems, April-May 1995, pp. 231–234.
J. M. Rabaey, M. Pedram, Low Power Design Methodologies, Kluwer Academic Publishers, 1996.
A. Raghunathan, N. Jha, “Behavioral synthesis for low power”, International Conference Computer Design, October 1994, pp. 318–322.
A. Raghunathan, N. Jha, “An ILP formulation for low power based on minimizing switched capacitance during data path allocation”, IEEE International Symposium Circuits and Systems, April-May 1995, pp. 1069–1073.
N. Sankarayya, K. Roy, D. Bhattacharya, “Algorithms for low power and high speed FIR filter realization using differential coefficients”, IEEE Transactions Circuits and Systems II, vol. 44, pp. 488–497, June 1997.
D. Shin, K. Choi, “Low power high level synthesis by increasing data correlation”, ACM/IEEE International Symposium Low Power Electronics and Design, August 1997, pp. 62–67.
E. P. Simoncelli, E. H. Adelson, “Subband transforms” Subband Image Coding, editor John Woods, Kluwer Academic Publishers, 1990.
W. Smith, J. Smith, Handbook of Real-Time Fast Fourier Transforms, IEEE Press, 1995.
S. Theoharis, G. Theodoridis, N. Zervas and C. Goutis, “Accurate and fast power estimation of large combinational circuits”, IEEE Workshop Power and Timing Modeling, Optimization and Simulation, October 1999, pp 199–208.
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Masselos, K., Goutis, C.E. (2000). Power Efficient Synthesis of Sum-of-Products Computations. In: Catthoor, F. (eds) Unified low-power design flow for data-dominated multi-media and telecom applications. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-3182-8_7
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DOI: https://doi.org/10.1007/978-1-4757-3182-8_7
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