Abstract
A methodology is presented for predicting the jitter performance of a PLL using simulation that is both accurate and efficient. The methodology begins by characterizing the noise behavior of the blocks that make up the PLL using transistor-level simulation. For each block, the jitter is extracted and provided as a parameter to behavioral models for inclusion in a high-level simulation of the entire PLL. This approach is efficient enough to be applied to complex systems, such as frequency synthesizers with large divide ratios or fractional-N synthesizers.
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© 1997 Springer Science+Business Media Dordrecht
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Kundert, K. (1997). Modeling and Simulation of Jitter in Phase-Locked Loops. In: van de Plassche, R.J., Huijsing, H.H., Sansen, W. (eds) Analog Circuit Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2602-2_16
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DOI: https://doi.org/10.1007/978-1-4757-2602-2_16
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-5185-4
Online ISBN: 978-1-4757-2602-2
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