Abstract
This paper describes techniques for achieving low power in a bipolar or BiCMOS synthesizer chip. The introductory material describes two types of fractional-N synthesizers and how these synthesizers could be used to reduce overall power consumption in a portable radio handset. The rest of the paper provides some tutorial review of bipolar logic design with some refinements for low power. The low power design is compared to previous versions in two different fabrication processes.
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© 1996 Springer Science+Business Media Dordrecht
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Riley, T.A.D., Copeland, M.A. (1996). A 2 GHz Low-Power Frequency Synthesizer. In: Huijsing, J.H., van de Plassche, R.J., Sansen, W.M.C. (eds) Analog Circuit Design. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2462-2_18
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DOI: https://doi.org/10.1007/978-1-4757-2462-2_18
Publisher Name: Springer, Boston, MA
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