Abstract
MiniSim is a description of a very simplified gate level simulator. Only three primitives have been included: a nand gate, a D positive edge-triggered flip flop, and a wire that handles the full strength algebra that is used in Verilog. All primitive timing is unit delay, and a record is kept of the stimulus pattern number and simulation time within each pattern. Each primitive is limited to two inputs and one output that has a maximum fanout of two.
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© 1995 Springer Science+Business Media New York
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Thomas, D.E., Moorby, P.R. (1995). Three Large Examples. In: The Verilog® Hardware Description Language. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2365-6_7
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DOI: https://doi.org/10.1007/978-1-4757-2365-6_7
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4757-2367-0
Online ISBN: 978-1-4757-2365-6
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