Abstract
Due the computational requirements of the video standards (H.261 and MPEG), early hardware implementations were multichip designs, where each major component such as the DCT processor and the variable-length coder was a separate chip. For example, in 1992, NEC introduced a three-chip set for MPEG-1 video encoding and decoding. The three ICs were an interframe coder (required only for video encoding), a transform and quantization processor, and a variable-length coder. Operating at 27 MHz, the chip set could process SIF resolution frames at 30 frames/s.
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© 1995 Springer Science+Business Media New York
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Bhaskaran, V., Konstantinides, K. (1995). Integrated Circuits for Video Coders. In: Image and Video Compression Standards. The Springer International Series in Engineering and Computer Science, vol 334. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2358-8_14
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DOI: https://doi.org/10.1007/978-1-4757-2358-8_14
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4757-2360-1
Online ISBN: 978-1-4757-2358-8
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