New RF Devices Based on High Precision CMOS Time-to-Digital and Digital-to-Time Converters

Abstract

The implementation of FM/PM demodulation based on direct cycle time measurement is feasible and attractive way to integrate FM receivers. Cycle time measurement is based on CMOS delay lines used as Time-to-Digital Converters (TDC). An experimental chip shows performance, size and current consumption comparable with the traditional quadrature phase shifter based IF/FM demodulator circuits and the level of achievable integration to be much better.

The use of CMOS delay lines as Digital-to-Time Converters (DTC) together with interpolation principle makes it possible control time intervals down to a few pico seconds. The interpolating phase locked loop frequency synthesizer, (IDPLL), is shown capable to adjust the phase of up to 2 GHz RF signals down to a small fraction of cycle time, thus facilitating small frequency steps, fast switching and settling together with low noise, and finally a digitally controllable, simple means for phase and frequency modulation.

With the current state-of-the art 63/64 tap CMOS delay lines with 40 ns range show an accuracy better than ± 0.5 ns which, in turn, results in an FM demodulator and an IDPLL synthesizer performance meeting radio telephony requirements.