Abstract
The goal of scheduling is to map the register transfers in the low-level signal flow graph g into discrete time slots, called control steps. The graph g is engrafted upon a particular data path configuration and contains primitive operations only. The amount of parallelism in the data path is used as a constraint to convert the applicative, maximally parallel signal-flow graph into a procedural description with a proper sequence of the register transfers, i.e., the schedule.
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© 1993 Springer Science+Business Media Dordrecht
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Vanhoof, J., Van Rompaey, K., Bolsens, I., Goossens, G., De Man, H. (1993). Scheduling. In: High-Level Synthesis for Real-Time Digital Signal Processing. The Springer International Series in Engineering and Computer Science, vol 216. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2222-2_6
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DOI: https://doi.org/10.1007/978-1-4757-2222-2_6
Publisher Name: Springer, Boston, MA
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