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A CMOS Time to Digital Converter with Analog Memory for High Energy Physics Particle Detectors

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Supercollider 5

Abstract

A data driven TDC (Time to Digital Converter) has been designed and fabricated in HP’s 1.2 μm nwell CMOS process. The circuit was designed to work with the straw tube electronics of the Superconducting Supercollider (SSC), where we wish to measure the arrival time of electrons at a sense wire. The TCCAMU (Time to Charge Converter with an Analog Memory Unit) measures the time between an edge of the system clock and the leading edge of an asynchronous signal, and then gives a digital output representing that time measurement. Analog data sparsification occurs before the digitization with the help of an analog Level 1 / Level 2 storage system; Level 1 to Level 2 data transfers are virtual, in the sense that one swaps capacitor addresses instead of moving charge.

Two separate fabrication runs resulted in chips that have ∼108 ps / LSB resolution for any particular storage location. The measurement range is 8 - 24 ns, but adding digital logic to count the reference clock will extend the range to ∼ 1 second.

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References

  1. A. Stevens, “A time-to-voltage converter with analog memory for colliding beam detectors,” IEEE JSSC, pp. 1748-1752, December 1989.

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  2. A. Stevens, “A fast low-power time-to-voltage converter for high luminosity collider detectors, IEEE Trans. Nucl. Sci., vol. 36, pp. 517–521, 1989.

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  3. Y. Arai, “A CMOS four-channel x IK time memory LSI with 1-ns/b resolution,” IEEE JSSC, pp. 359-364, March 1992.

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  4. L. Callewaert, “Front end and signal processing electronics for detectors at high luminosity colliders,” IEEE Trans. Nucl. sci., vol. 36, pp. 446–457, February 1989.

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  5. Dan Porat, “Review of sub-nanosecond time-interval measurements,” IEEE Trans. Nucl. Sci. pp. 36-51, 1973.

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© 1994 Springer Science+Business Media New York

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Gerds, E.J., Van der Spiegel, J., Williams, H.H., Van Berg, R. (1994). A CMOS Time to Digital Converter with Analog Memory for High Energy Physics Particle Detectors. In: Hale, P. (eds) Supercollider 5. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-2439-7_11

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  • DOI: https://doi.org/10.1007/978-1-4615-2439-7_11

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4613-6036-0

  • Online ISBN: 978-1-4615-2439-7

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