Abstract
Once the clock constraints have been applied, all the register to register paths can be timed. Now, the delay constraints have to be applied on non-clock ports. If input and output port constraints are not specified, timing analysis tools assume a highly optimistic timing requirements on the interfaces. They assume the combinational logic inside the block can have the entire period to itself and leave nothing for the portion of the signal outside the block.
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© 2013 Springer Science+Business Media New York
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Gangadharan, S., Churiwala, S. (2013). Port Delays. In: Constraining Designs for Synthesis and Timing Analysis. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-3269-2_9
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DOI: https://doi.org/10.1007/978-1-4614-3269-2_9
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Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4614-3268-5
Online ISBN: 978-1-4614-3269-2
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