Abstract
The goal of this paper is to exemplify a conceptual framework, namely the theory of finite state machines, for the VLSI design process. We start from a functional description of the system to be realized and achieve a (semi)systolic array in a formal way. Moreover, the resulting designs are correct by their mere construction.
A related paper [14] is presented to the International Conference on Systolic Arrays, San Diego, May 1988
partially supported by Siemens AG
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© 1990 Springer-Verlag Berlin Heidelberg
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Payer, M. (1990). Finite state machine theory as a tool for construction of systolic arrays. In: Pichler, F., Moreno-Diaz, R. (eds) Computer Aided Systems Theory — EUROCAST '89. EUROCAST 1989. Lecture Notes in Computer Science, vol 410. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-52215-8_19
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DOI: https://doi.org/10.1007/3-540-52215-8_19
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