Abstract
As the importance of cache performance increases, allowing software to assist in cache management decisions becomes an attractive alternative. This paper focuses primarily on a mechanism for software to convey information to the memory hierarchy. We introduce a single instruction—called TAG—that can annotate subsequent memory references with a number of bits, thus avoiding major modifications to the instruction set. Simulation results show that annotating all memory reference instructions in the SPEC95 benchmarks increases execution time between 0% and 2% for both statically and dynamically scheduleded processors. We show that exposing cache management mechanisms to software can decrease the execution time of three media benchmarks (epic, pegwit, ijpeg) between 11% and 17% speedups on a 4-issue dynamically scheduled processor.
Chapter PDF
Keywords
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
References
S.G. Abraham, R.A. Sugumar, D. Windheiser, B.R. Rau, and R. Gupta. Predictability of load/store instruction latencies. Proceedings of the 26th Annual International Symposium on Microarchitecture, pages 139–152, December 1993.
D.C. Burger, T.M. Austin, and S. Bennett. Evaluating future microprocessors-the simplescalar tool set. Technical Report 1308, University of Wisconsin-Madison Computer Sciences Department, July 1996.
A. Gonzalez, C. Aliagas, and M. Valero. A data cache with multiple caching strategies tuned to different types of locality. In ACM 1995 International Conference on Supercomputing, pages 338–347, 1995.
A.R. Lebeck and D.A. Wood. Cache profiling and the spec benchmarks: A case study. IEEE COMPUTER, 27(10):15–26, October 1994.
A. Srivastava and A. Eustace. Atom a system for building customized program analysis tools. In Proceedings of the SIGPLAN’ 94 Conference on Programming Language Design and Implementation, pages 196–205, June 1994.
G. Tyson, M. Farrens, J. Matthews, and A.R. Pleszkun. A modified approach to data cache management. In Proceedings of the 28th Annual International Symposium on Microarchitecture, Dec. 1995.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1999 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Lebeck, A.R., Raymond, D.R., Yang, CL., Thottethodi, M.S. (1999). Annotated Memory References: A Mechanism for Informed Cache Management. In: Amestoy, P., et al. Euro-Par’99 Parallel Processing. Euro-Par 1999. Lecture Notes in Computer Science, vol 1685. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48311-X_177
Download citation
DOI: https://doi.org/10.1007/3-540-48311-X_177
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-66443-7
Online ISBN: 978-3-540-48311-3
eBook Packages: Springer Book Archive