Static Crosstalk-Noise Analysis

For Deep Sub-Micron Digital Designs

  • Pinhong Chen
  • Desmond A. Kirkpatrick
  • Kurt Keutzer

Table of contents

About this book


As the feature size decreases in deep sub-micron designs, coupling capacitance becomes the dominant factor in total capacitance. The resulting crosstalk noise may be responsible for signal integrity issues and significant timing variation. Traditionally, static timing analysis tools have ignored cross coupling effects between wires altogether. Newer tools simply approximate the coupling capacitance by a 2X Miller factor in order to compute the worst case delay. The latter approach not only reduces delay calculation accuracy, but can also be shown to underestimate the delay in certain scenarios.
This book describes accurate but conservative methods for computing delay variation due to coupling. Furthermore, most of these methods are computationally efficient enough to be employed in a static timing analysis tool for complex integrated digital circuits. To achieve accuracy, a more accurate computation of the Miller factor is derived. To achieve both computational efficiency and accuracy, a variety of mechanisms for pruning the search space are detailed, including:

-Spatial pruning - reducing aggressors to those in physical proximity,
-Electrical pruning - reducing aggressors by electrical strength,
-Temporal pruning - reducing aggressors using timing windows,
-Functional pruning - reducing aggressors by Boolean functional analysis.


CMOS Olson Signal algorithms complexity construction digital design interconnect mechanism model modeling network optimization published tables

Authors and affiliations

  • Pinhong Chen
    • 1
  • Desmond A. Kirkpatrick
    • 2
  • Kurt Keutzer
    • 3
  1. 1.Cadence Design Systems, Inc.USA
  2. 2.Intel CorporationUSA
  3. 3.University of CaliforniaBerkeley

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