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Static Crosstalk-Noise Analysis

For Deep Sub-Micron Digital Designs

  • Book
  • © 2004

Overview

Authors:
  1. Pinhong Chen

    1. Cadence Design Systems, Inc., USA

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    You can also search for this author in PubMed   Google Scholar

  2. Desmond A. Kirkpatrick

    1. Intel Corporation, USA

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  3. Kurt Keutzer

    1. University of California, Berkeley

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Table of contents (7 chapters)

  1. Front Matter

    Pages i-xviii
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  2. Introduction

    Pages 1-14

  3. Miller Factor Computation for Coupling Delay

    Pages 15-35

  4. Convergence of Switching Window Computation

    Pages 37-60

  5. Speeding-Up Switching Window Computation

    Pages 61-77

  6. Refinement of Switching Windows

    Pages 79-90

  7. Functional Crosstalk Analysis

    Pages 91-106

  8. Conclusions

    Pages 107-108

  9. Back Matter

    Pages 109-113
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Keywords

About this book

As the feature size decreases in deep sub-micron designs, coupling capacitance becomes the dominant factor in total capacitance. The resulting crosstalk noise may be responsible for signal integrity issues and significant timing variation. Traditionally, static timing analysis tools have ignored cross coupling effects between wires altogether. Newer tools simply approximate the coupling capacitance by a 2X Miller factor in order to compute the worst case delay. The latter approach not only reduces delay calculation accuracy, but can also be shown to underestimate the delay in certain scenarios.
This book describes accurate but conservative methods for computing delay variation due to coupling. Furthermore, most of these methods are computationally efficient enough to be employed in a static timing analysis tool for complex integrated digital circuits. To achieve accuracy, a more accurate computation of the Miller factor is derived. To achieve both computational efficiency and accuracy, a variety of mechanisms for pruning the search space are detailed, including:

-Spatial pruning - reducing aggressors to those in physical proximity,
-Electrical pruning - reducing aggressors by electrical strength,
-Temporal pruning - reducing aggressors using timing windows,
-Functional pruning - reducing aggressors by Boolean functional analysis.

Reviews

"Finally, a detailed analysis of the silicon interconnect coupling problem! This book not only addresses the coupling noise problem, but formulates and proposes usable CAD algorithms. Since the uncertainty in silicon design performance and reliability due to increasing coupling noise will only get worse each silicon generation, these algorithms will quickly find a gratefulhome in many CAD solutions."
(William J. Grundmann, Intel Fellow, Intel Corporation)
"All signoff analyses - timing, coupling, power, temperature, and reliability - rely on the analysis of crosstalk noise. This book is an important contribution to the field: it provides a synthesis of analytic bounding of crosstalk effects, switching window convergence, and other recent elements of crosstalk methodology. It provides a level of understanding that will be essential for researchers, developers, and users of leading EDA tools going forward."
(Andrew B. Kahng, Professor of CSE and ECE, University of California, San Diego)

Authors and Affiliations

  • Cadence Design Systems, Inc., USA

    Pinhong Chen

  • Intel Corporation, USA

    Desmond A. Kirkpatrick

  • University of California, Berkeley

    Kurt Keutzer

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