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Interconnect-Centric Design for Advanced SoC and NoC

  • Jari Nurmi
  • Hannu Tenhunen
  • Jouni Isoaho
  • Axel Jantsch

Table of contents

  1. Front Matter
    Pages i-vii
  2. Physical and Electrical Issues

    1. Front Matter
      Pages 1-1
    2. Li-Rong Zheng, Hannu Tenhunen
      Pages 25-54
    3. Tero Nurmi, Jian Liu, Dinesh Pamunuwa, Tapani Ahonen, Li-Rong Zheng, Jouni Isoaho et al.
      Pages 55-84
    4. Magdy A. El-Moursy, Eby G. Friedman
      Pages 85-124
  3. Logical and Architectural Issues

    1. Front Matter
      Pages 153-153
    2. Heiko Zimmer, Axel Jantsch
      Pages 155-176
    3. Paul P. Sotiriadis
      Pages 177-205
    4. Vesa Lahtinen, Erno Salminen, Kimmo Kuusilinna, Timo D. Hämäläinen
      Pages 207-230
    5. David Sigüuenza-Tortosa, Jari Nurmi
      Pages 231-251
    6. Heikki Kariniemi, Jari Nurmi
      Pages 253-282
  4. Design Methodology and Tools

    1. Front Matter
      Pages 283-283
    2. Pasi Liljeberg, Johanna Tuominen, Sampo Tuuna, Juha Plosila, Jouni Isoaho
      Pages 285-313
    3. Juha Plosila, Tiberiu Seceleanu, Kaisa Sere
      Pages 315-340
    4. Jan Madsen, 1Shankar Mahadevan, Kashif Virk
      Pages 341-365
  5. Application Cases

    1. Front Matter
      Pages 397-397
    2. Kees Goossens, Om Prakash Gangwal, Jens Röover, A.P. Niranjan
      Pages 399-423
    3. Tapani Ahonen, Seppo Virtanen, Juha Kylliäainen, Dragos Truscan, Tuukka Kasanko, David Sigäuenza-Tortosa et al.
      Pages 425-453

About this book

Introduction

In Interconnect-centric Design for Advanced SoC and NoC, we have tried to create a comprehensive understanding about on-chip interconnect characteristics, design methodologies, layered views on different abstraction levels and finally about applying the interconnect-centric design in system-on-chip design.
Traditionally, on-chip communication design has been done using rather ad-hoc and informal approaches that fail to meet some of the challenges posed by next-generation SOC designs, such as performance and throughput, power and energy, reliability, predictability, synchronization, and management of concurrency. To address these challenges, it is critical to take a global view of the communication problem, and decompose it along lines that make it more tractable. We believe that a layered approach similar to that defined by the communication networks community should also be used for on-chip communication design.
The design issues are handled on physical and circuit layer, logic and architecture layer, and from system design methodology and tools point of view. Formal communication modeling and refinement is used to bridge the communication layers, and network-centric modeling of multiprocessor on-chip networks and socket-based design will serve the development of platforms for SoC and NoC integration. Interconnect-centric Design for Advanced SoC and NoC is concluded by two application examples: interconnect and memory organization in SoCs for advanced set-top boxes and TV, and a case study in NoC platform design for more generic applications.

Keywords

Routing SoC architecture communication integrated circuit layers modeling network on chip (NoC) simulation single-electron transistor system on chip (SoC)

Editors and affiliations

  • Jari Nurmi
    • 1
  • Hannu Tenhunen
    • 2
  • Jouni Isoaho
    • 3
  • Axel Jantsch
    • 2
  1. 1.Tampere University of TechnologyFinland
  2. 2.Royal Institute of TechnologySweden
  3. 3.University of TurkuFinland

Bibliographic information

  • DOI https://doi.org/10.1007/b117241
  • Copyright Information Springer Science + Business Media, Inc. 2005
  • Publisher Name Springer, Boston, MA
  • eBook Packages Engineering
  • Print ISBN 978-1-4020-7835-4
  • Online ISBN 978-1-4020-7836-1
  • Buy this book on publisher's site
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