The e Hardware Verification Language

  • Sasan Iman
  • Sunita Joshi

Table of contents

  1. Front Matter
    Pages i-xxii
  2. Introduction

    1. Pages 1-7
  3. Verification Methodologies and Environment Architecture

    1. Front Matter
      Pages 9-9
  4. All About e

    1. Front Matter
      Pages 51-51
  5. Topology and Stimulus Generation

    1. Front Matter
      Pages 103-103
    2. Pages 105-120
    3. Pages 137-161
  6. Response Collection, Data Checking, and Property Monitoring

    1. Front Matter
      Pages 163-163
    2. Pages 165-188
    3. Pages 189-198
    4. Pages 199-211
    5. Pages 213-222
  7. Coverage Modeling and Measurement

    1. Front Matter
      Pages 223-223
    2. Pages 225-243
    3. Pages 245-263
  8. e Code Reuse

    1. Front Matter
      Pages 265-265
    2. Pages 267-278
    3. Pages 279-301
  9. Back Matter
    Pages 303-349

About this book


I am glad to see this new book on the e language and on verification. I am especially glad to see a description of the e Reuse Methodology (eRM). The main goal of verification is, after all, finding more bugs quicker using given resources, and verification reuse (module-to-system, old-system-to-new-system etc. ) is a key enabling component. This book offers a fresh approach in teaching the e hardware verification language within the context of coverage driven verification methodology. I hope it will help the reader und- stand the many important and interesting topics surrounding hardware verification. Yoav Hollander Founder and CTO, Verisity Inc. Preface This book provides a detailed coverage of the e hardware verification language (HVL), state of the art verification methodologies, and the use of e HVL as a facilitating verification tool in implementing a state of the art verification environment. It includes comprehensive descriptions of the new concepts introduced by the e language, e language syntax, and its as- ciated semantics. This book also describes the architectural views and requirements of verifi- tion environments (randomly generated environments, coverage driven verification environments, etc. ), verification blocks in the architectural views (i. e. generators, initiators, c- lectors, checkers, monitors, coverage definitions, etc. ) and their implementations using the e HVL. Moreover, the e Reuse Methodology (eRM), the motivation for defining such a gui- line, and step-by-step instructions for building an eRM compliant e Verification Component (eVC) are also discussed.


Generator Hardware architecture modeling programming programming language

Authors and affiliations

  • Sasan Iman
    • 1
  • Sunita Joshi
    • 1
  1. 1.SiMantis Inc.Santa Clara

Bibliographic information

  • DOI
  • Copyright Information Springer Science + Business Media, Inc. 2004
  • Publisher Name Springer, Boston, MA
  • eBook Packages Springer Book Archive
  • Print ISBN 978-1-4020-8023-4
  • Online ISBN 978-1-4020-8024-1
  • Buy this book on publisher's site
Industry Sectors
IT & Software