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Direct Transistor-level Layout for Digital Blocks

  • Prakash Gopalakrishnan
  • Rob A. Rutenbar

Table of contents

  1. Front Matter
    Pages i-ix
  2. Pages 1-12
  3. Pages 35-48
  4. Pages 103-106
  5. Back Matter
    Pages 107-125

About this book

Introduction

Cell-based design methodologies have dominated layout generation of digital circuits. Unfortunately, the growing demands for transparent process portability, increased performance, and low-level device sizing for timing/power are poorly handled in a fixed cell library.
Direct Transistor-Level Layout For Digital Blocks proposes a direct transistor-level layout approach for small blocks of custom digital logic as an alternative that better accommodates demands for device-level flexibility. This approach captures essential shape-level optimizations, yet scales easily to netlists with thousands of devices, and incorporates timing optimization during layout. The key idea is early identification of essential diffusion-merged MOS device groups, and their preservation in an uncommitted geometric form until the very end of detailed placement. Roughly speaking, essential groups are extracted early from the transistor-level netlist, placed globally, optimized locally, and then finally committed each to a specific shape-level form while concurrently optimizing for both density and routability.
The essential flaw in prior efforts is an over-reliance on geometric assumptions from large-scale cell-based layout algorithms. Individual transistors may seem simple, but they do not pack as gates do. Algorithms that ignore these shape-level issues suffer the consequences when thousands of devices are poorly packed. The approach described in this book can pack devices much more densely than a typical cell-based layout.
Direct Transistor-Level Layout For Digital Blocks is a comprehensive reference work on device-level layout optimization, which will be valuable to CAD tool and circuit designers.

Keywords

Computer-Aided Design (CAD) Layout Transistor algorithms circuit design logic optimization

Authors and affiliations

  • Prakash Gopalakrishnan
    • 1
  • Rob A. Rutenbar
    • 2
  1. 1.Neolinear, Inc.USA
  2. 2.Carnegie Mellon UniversityItaly

Bibliographic information

  • DOI https://doi.org/10.1007/b117054
  • Copyright Information Springer Science + Business Media, Inc. 2005
  • Publisher Name Springer, Boston, MA
  • eBook Packages Engineering
  • Print ISBN 978-1-4020-7665-7
  • Online ISBN 978-1-4020-8063-0
  • Buy this book on publisher's site
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