System-on-a-Chip Verification

1. Front Matter

   Pages i-xx

   PDF

2. Introduction

   Pages 1-43

3. System-level Verification

   Pages 45-66

4. Block-level Verification

   Pages 67-127

5. Analog/Mixed Signal Simulation

   Pages 129-151

6. Simulation

   Pages 153-234

7. Hardware/Software Co-verification

   Pages 235-315

8. Static Netlist Verification

   Pages 317-345

9. Physical Verification and Design Sign-off

   Pages 347-358

10. Back Matter

    Pages 361-372

    PDF

System-On-a-Chip Verification: Methodology and Techniques is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign- off. The topics covered include Introduction to the SOC design and verification aspects, System level verification in brief, Block level verification, Analog/mixed signal simulation, Simulation, HW/SW Co-verification, Static netlist verification, Physical verification, and Design sign-off in brief. All the verification aspects are illustrated with a single reference design for Bluetooth application.
System-On-a-Chip Verification: Methodology and Techniques takes a systematic approach that covers the following aspects of verification strategy in each chapter:

1. Explanation of the objective involved in performing verification after a given design step;
2. Features of options available;
3. When to use a particular option;
4. How to select an option; and
5. Limitations of the option.

This exciting new book will be of interest to all designers and test professionals.

• Bluetooth
• FPGA
• Field Programmable Gate Array
• Hardware
• Signal
• Software
• analog
• calculus
• design
• integrated circuit
• model
• model checking
• simulation
• system on chip (SoC)
• verification

• Cadence Design Systems, Inc., USA

  Prakash Rashinkar, Peter Paterson, Leena Singh

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