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Time-interleaved Analog-to-Digital Converters

  • Book
  • © 2011

Overview

  • Comprehensive theoretical analysis of the building blocks of a time-interleaved ADC
  • Easy readable with a lot of practical design techniques aiming at both industry and research
  • Focus on low-power design techniques including successive approximation ADCs
  • Presentation of a state-of-the-art high-speed low-power 1.8 GS/s ADC
  • Includes supplementary material: sn.pub/extras

Part of the book series: Analog Circuits and Signal Processing (ACSP)

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Table of contents (5 chapters)

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About this book

Time-interleaved Analog-to-Digital Converters describes the research performed on low-power time-interleaved ADCs. A detailed theoretical analysis is made of the time-interleaved Track & Hold, since it must be capable of handling signals in the GHz range with little distortion, and minimal power consumption. Timing calibration is not attractive, therefore design techniques are presented which do not require timing calibration.

The design of power efficient sub-ADCs is addressed with a theoretical analysis of a successive approximation converter and a pipeline converter. It turns out that the first can consume about 10 times less power than the latter, and this conclusion is supported by literature.

Time-interleaved Analog-to-Digital Converters describes the design of a high performance time-interleaved ADC, with much attention for practical design aspects, aiming at both industry and research. Measurements show best-inclass performance with a sample-rate of 1.8 GS/s, 7.9 ENOBs and a power efficiency of 1 pJ/conversion-step.

Authors and Affiliations

  • Axiom IC, Enschede, Netherlands

    Simon Louwsma

  • Axiom IC / University of Twente, Enschede, Netherlands

    Ed Tuijl

  • MESA + Institute, University of Twente, Enschede, Netherlands

    Bram Nauta

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