Reconfigurable Computing: Architectures, Tools and Applications

1. Session 5: Design Tools 1

   1. TROUTE: A Reconfigurability-Aware FPGA Router

      • Karel Bruneel, Dirk Stroobandt

      Pages 207-218

   2. Space and Time Sharing of Reconfigurable Hardware for Accelerated Parallel Processing

      • Esam El-Araby, Vikram K. Narayana, Tarek El-Ghazawi

      Pages 219-230

   3. Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture

      • Ganghee Lee, Seokhyun Lee, Kiyoung Choi, Nikil Dutt

      Pages 231-243

2. Session 6: Design Tools 2

   1. Design Automation for Reconfigurable Interconnection Networks

      • Hongbing Fan, Yu-Liang Wu, Chak-Chung Cheung

      Pages 244-256

   2. A Framework for Enabling Fault Tolerance in Reconfigurable Architectures

      • Kostas Siozios, Dimitrios Soudris, Dionisios Pnevmatikatos

      Pages 257-268

   3. QUAD – A Memory Access Pattern Analyser

      • S. Arash Ostadzadeh, Roel J. Meeuws, Carlo Galuzzi, Koen Bertels

      Pages 269-281

   4. Hierarchical Loop Partitioning for Rapid Generation of Runtime Configurations

      • Siew-Kei Lam, Yun Deng, Jian Hu, Xilong Zhou, Thambipillai Srikanthan

      Pages 282-293

3. Session 7: Applications 3

   1. Reconfigurable Computing and Task Scheduling for Active Storage Service Processing

      • Yu Zhang, Dan Feng

      Pages 294-305

   2. A Reconfigurable Disparity Engine for Stereovision in Advanced Driver Assistance Systems

      • Mehdi Darouich, Stephane Guyetant, Dominique Lavenier

      Pages 306-317

   3. A Modified Merging Approach for Datapath Configuration Time Reduction

      • Mahmood Fazlali, Ali Zakerolhosseini, Georgi Gaydadjiev

      Pages 318-328

4. Posters

   1. Reconfigurable Computing Education in Computer Science

      • Abdulhadi Shoufan, Sorin Alexander Huss

      Pages 329-336

   2. Hardware Implementation of the Orbital Function for Quantum Chemistry Calculations

      • Maciej Wielgosz, Ernest Jamro, Pawel Russek, Kazimierz Wiatr

      Pages 337-342

   3. Reconfigurable Polyphase Filter Bank Architecture for Spectrum Sensing

      • Suhaib A. Fahmy, Linda Doyle

      Pages 343-350

   4. Systolic Algorithm Mapping for Coarse Grained Reconfigurable Array Architectures

      • Kunjan Patel, C. J. Bleakley

      Pages 351-357

   5. A GMM-Based Speaker Identification System on FPGA

      • Phak Len Eh Kan, Tim Allen, Steven F. Quigley

      Pages 358-363

   6. An FPGA-Based Real-Time Event Sampler

      • Niels Penneman, Luc Perneel, Martin Timmerman, Bjorn De Sutter

      Pages 364-371

   7. A Performance Evaluation of CUBE: One-Dimensional 512 FPGA Cluster

      • Masato Yoshimi, Yuri Nishikawa, Mitsunori Miki, Tomoyuki Hiroyasu, Hideharu Amano, Oskar Mencer

      Pages 372-381

   8. An Analysis of Delay Based PUF Implementations on FPGA

      • Sergey Morozov, Abhranil Maiti, Patrick Schaumont

      Pages 382-387

   9. Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable Processor

      • Kazuya Tanigawa, Ken’ichi Umeda, Tetsuo Hironaka

      Pages 388-393

   10. FPGA Implementation of QR Decomposition Using MGS Algorithm

       • Akkarat Boonpoonga, Sompop Janyavilas, Phaophak Sirisuk, Monai Krairiksh

       Pages 394-399

Recon?gurable computing (RC) systems have generated considerable interest in the embedded and high-performance computing communities over the past two decades, with ?eld programmable gate arrays (FPGAs) as the leading techn- ogy at the helm of innovation in this discipline. Achieving orders of magnitude performance and power improvements using FPGAs over traditional microp- cessorsis not uncommon for well-suitedapplications. But even with two decades of research and technological advances, FPGA design still presents a subst- tial challenge and often necessitates hardware design expertise to exploit its true potential. Although the challenges to address the design productivity - sues are steep, the promise and the potential of the RC technology in terms of performance, power, size, and versatility continue to attract application design engineers and RC researchers alike. The International Symposium on Applied Recon?gurable Computing (ARC) aims to bring together researchers and practitioners of RC systems with an emphasis on practical applications and design methodologies of this promising technology. This year’s ARC symposium (The sixth ARC symposium) was held in Bangkok, Thailand during March 17–19, 2010, and attracted papers in three primary focus areas:RC applications, RC architectures, and RC design meth- ologies.

• 3D graphics
• ARC
• Debugging
• Router
• Routing
• Scheduling
• algorithms
• design
• algorithm analysis and problem complexity

• Department of Electronic Engineering, Mahanakorn University of Technology, Bangkok, Thailand

  Phaophak Sirisuk

• Department of Electronic Engineering, National University of Ireland, Galway, Ireland

  Fearghal Morgan

• Department of Electrical and Computer Engineering, The George Washington University, Washington, USA

  Tarek El-Ghazawi

• Department of Information and Computer Science, Yokohama, Keio University, Kanagawa, Japan

  Hideharu Amano

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