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Robotic Exploration and Landmark Determination

Hardware-Efficient Algorithms and FPGA Implementations

  • Authors
  • K.¬†Sridharan
  • Panakala Rajesh¬†Kumar

Part of the Studies in Computational Intelligence book series (SCI, volume 81)

Table of contents

  1. Front Matter
    Pages I-XIV
  2. Pages 3-12
  3. Pages 13-23
  4. Pages 87-90
  5. Back Matter
    Pages 91-137

About this book

Introduction

Much of the research effort in mobile robots in the recent past has been on sensing and design of time-efficient algorithms for tasks such as localization, mapping and navigation. Mobile robots typically employ an embedded computer for high level computations. As applications of robots expand, there is a need to investigate architecturally efficient choices for this embedded computing platform. In particular, it is valuable to process data to obtain time, space and energy-efficient solutions for various robotic tasks.

This book presents hardware-efficient algorithms and FPGA implementations for two robotic tasks, namely exploration and landmark determination. The work identifies scenarios for mobile robotics where parallel processing and selective shutdown offered by FPGAs are invaluable. The book proceeds to systematically develop memory-driven VLSI architectures for both the tasks. The architectures are ported to a low-cost FPGA with a fairly small number of system gates. A robot fabricated with this FPGA on-board serves to validate the efficacy of the approach. Numerous experiments with the robot are reported.

Keywords

FPGA VLSI algorithm algorithms architecture mobile robot navigation robot robotics sensing

Bibliographic information

  • DOI https://doi.org/10.1007/978-3-540-75394-0
  • Copyright Information Springer-Verlag Berlin Heidelberg 2008
  • Publisher Name Springer, Berlin, Heidelberg
  • eBook Packages Engineering
  • Print ISBN 978-3-540-75393-3
  • Online ISBN 978-3-540-75394-0
  • Series Print ISSN 1860-949X
  • Buy this book on publisher's site
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