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A Pipelined Multi-core MIPS Machine

Hardware Implementation and Correctness Proof

  • Mikhail Kovalev
  • Silvia M. Müller
  • Wolfgang J. Paul

Part of the Lecture Notes in Computer Science book series (LNCS, volume 9000)

Table of contents

  1. Front Matter
  2. Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul
    Pages 1-6
  3. Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul
    Pages 7-27
  4. Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul
    Pages 29-82
  5. Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul
    Pages 83-98
  6. Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul
    Pages 99-115
  7. Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul
    Pages 117-160
  8. Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul
    Pages 161-206
  9. Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul
    Pages 207-310
  10. Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul
    Pages 311-344
  11. Back Matter

About this book

Introduction

This monograph is based on the third author's lectures on computer architecture, given in the summer semester 2013 at Saarland University, Germany. It contains a gate level construction of a multi-core machine with pipelined MIPS processor cores and a sequentially consistent shared memory.

The book contains the first correctness proofs for both the gate level implementation of a multi-core processor and also of a cache based sequentially consistent shared memory. This opens the way to the formal verification of synthesizable hardware for multi-core processors in the future.

Constructions are in a gate level hardware model and thus deterministic. In contrast the reference models against which correctness is shown are nondeterministic. The development of the additional machinery for these proofs and the correctness proof of the shared memory at the gate level are the main technical contributions of this work.

Keywords

algebraic specification arithmetic logic unit automata states basic pipelined processor design basic sequential mips machine cache protocol automata finite state machines instruction set architecture memory embedding microprocessor without interlocked pipeline stages multi-bank ram multi-core next pc environment pipelining scheduling functions self destructing hardware software conditions solving equations

Authors and affiliations

  • Mikhail Kovalev
    • 1
  • Silvia M. Müller
    • 2
  • Wolfgang J. Paul
    • 3
  1. 1.Sirrix AGSaarbrückenGermany
  2. 2.IBM Germany Research and Development GmbHBöblingenGermany
  3. 3.Saarland UniversitySaarbrückenGermany

Bibliographic information

  • DOI https://doi.org/10.1007/978-3-319-13906-7
  • Copyright Information Springer International Publishing Switzerland 2014
  • Publisher Name Springer, Cham
  • eBook Packages Computer Science
  • Print ISBN 978-3-319-13905-0
  • Online ISBN 978-3-319-13906-7
  • Series Print ISSN 0302-9743
  • Series Online ISSN 1611-3349
  • Buy this book on publisher's site
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