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Low-Noise Low-Power Design for Phase-Locked Loops

Multi-Phase High-Performance Oscillators

  • Feng Zhao
  • Fa Foster Dai

Table of contents

  1. Front Matter
    Pages i-xiii
  2. Feng Zhao, Fa Foster Dai
    Pages 1-11
  3. Feng Zhao, Fa Foster Dai
    Pages 25-39
  4. Feng Zhao, Fa Foster Dai
    Pages 95-96

About this book

Introduction

This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the noise reduction techniques for fractional-N PLL design and introduces a novel capacitive-quadrature coupling technique for multi-phase signal generation.  The capacitive-coupling technique has been validated through silicon implementation and can provide low phase-noise and accurate I-Q phase matching, with low power consumption from a super low supply voltage.  Readers will be enabled to pick one of the most suitable QVCO circuit structures for their own designs, without additional effort to look for the optimal circuit structure and device parameters. 

Keywords

Clock Generation for Wireless Communication Frequency Synthesis for Phase-Locked Loops Low Power Design for Phase-Locked Loops Noise Reduction for Phase-Locked Loops Phase-Locked Loops Quadrature Oscillators Quadrature Signal Generation Wireless Communication

Authors and affiliations

  • Feng Zhao
    • 1
  • Fa Foster Dai
    • 2
  1. 1.Santa ClaraUSA
  2. 2.Department of Electrical and Computer EnAuburn UniversityAuburnUSA

Bibliographic information

  • DOI https://doi.org/10.1007/978-3-319-12200-7
  • Copyright Information Springer International Publishing Switzerland 2015
  • Publisher Name Springer, Cham
  • eBook Packages Engineering
  • Print ISBN 978-3-319-12199-4
  • Online ISBN 978-3-319-12200-7
  • Buy this book on publisher's site
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