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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

  • Book
  • © 2014

Overview

Authors:
  1. Brandon Noia

    1. ECE, Duke University, Durham, USA

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  2. Krishnendu Chakrabarty

    1. ECE, Duke University, Durham, USA

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    You can also search for this author in PubMed   Google Scholar

  • Provides a comprehensive guide to the challenges and solutions for the testing of TSV-based 3D stacked ICs
  • Includes in-depth explanation of key test and design-for-test technologies, emerging standards, and test- architecture and test-schedule optimizations
  • Encompasses all aspects of test as related to 3D ICs, including pre-bond and post-bond test as well as the test optimization and scheduling necessary to ensure that 3D testing remains cost-effective

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Table of contents (9 chapters)

  1. Front Matter

    Pages i-xviii
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  2. Introduction

    • Brandon Noia, Krishnendu Chakrabarty
    Pages 1-10

  3. Wafer Stacking and 3D Memory Test

    • Brandon Noia, Krishnendu Chakrabarty
    Pages 11-54

  4. Built-In Self-Test for TSVs

    • Brandon Noia, Krishnendu Chakrabarty
    Pages 55-79

  5. Pre-bond TSV Test Through TSV Probing

    • Brandon Noia, Krishnendu Chakrabarty
    Pages 81-113

  6. Pre-bond Scan Test Through TSV Probing

    • Brandon Noia, Krishnendu Chakrabarty
    Pages 115-135

  7. Overcoming the Timing Overhead of Test Architectures on Inter-Die Critical Paths

    • Brandon Noia, Krishnendu Chakrabarty
    Pages 137-158

  8. Post-Bond Test Wrappers and Emerging Test Standards

    • Brandon Noia, Krishnendu Chakrabarty
    Pages 159-180

  9. Test-Architecture Optimization and Test Scheduling

    • Brandon Noia, Krishnendu Chakrabarty
    Pages 181-237

  10. Conclusions

    • Brandon Noia, Krishnendu Chakrabarty
    Pages 239-240

  11. Back Matter

    Pages 241-245
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Keywords

About this book

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.

Authors and Affiliations

  • ECE, Duke University, Durham, USA

    Brandon Noia, Krishnendu Chakrabarty

About the authors

Krishnendu Chakrabarty is a Professor of Electrical and Computer Engineering at Duke University. He received his PhD from University of Michigan. He is a Fellow of IEEE and a Distinguished Engineer of ACM.

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